implementacion LTSpice en pyhton

This commit is contained in:
Oscar Suescun Elizalde 2025-04-07 12:43:28 +02:00
parent 72c38071b3
commit 8a19683b30
12 changed files with 147 additions and 59 deletions

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src/funcionesSim.py Normal file
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from PyLTSpice import SimRunner, SpiceEditor, RawRead
import numpy as np
import matplotlib.pyplot as plt
'''
Este codigo funciona sobre modelo.net
Para conseguir este archivo hay que ir al .asc con
el mismo nombre y ir View > SPICE Netlist. Esto
mostrara el codigo que se quiere. Se copia el codigo
y se pega en un file con extenion .net
'''
__author__ = 'Oscar Suescun'
def simular(tensionCap, Rtotal, Lbobina, Ctotal, lts_path, tSim = 100e-3, toff_sw = 1e-3, ton_mos = 1.5e-3):
'''
Funcion principal de simulacion.
Entradas Obligatorias:
- tensionCap -> Tension del capacitor
- Rtotal -> Resistencia total en el circuito (Rextra + Rbobina)
- Lbobina -> Inductancia de la bobina
- Ctotal -> capacidad del banco de capacitores
- lts_path -> directorio donde tienes el .exe de LTSpice
Entradas Opcionales:
- tSim -> tiempo total de simulacion (de normal 100ms)
- toff_sw -> tiempo que tarda la fuente en
desconectarse del capacitor (de normal 1ms)
- ton_mos -> tiempo que tarda el mosfet en abrir el gate
del mosfet de disparo (de normal 1.5ms)
Salida
resultados = {
'tiempo' : vector con el tiempo de simulacion
'vCap' : Vector con la tension entre Capacitor -> GND
'vBob' : Vector de tension atraves de la bobina
'iBob' : Vector con la corriente atraves de Bobina
}
'''
modeloSim = "src/simulador/modelo_transitorio.asc"
outDir = 'src/simulador'
## Hago la simulacion
simulador = SimRunner(output_folder=outDir, simulator=lts_path)
simulador.create_netlist(modeloSim)
netlist = SpiceEditor(modeloSim.replace('.asc', '.net'))
netlist.set_parameters(V = tensionCap,
R = Rtotal,
L = Lbobina,
C = Ctotal,
tSim = tSim,
toff_sw = toff_sw,
ton_mos = ton_mos)
simulador.run(netlist)
for raw_path, log_path in simulador:
raw = RawRead(raw_path)
try:
return{
'tiempo' : np.array(raw.get_trace('time')),
'vCap' : np.array(raw.get_trace('V(condensador)')),
'vBob' : np.array(raw.get_trace('V(V1)')) - np.array(raw.get_trace('V(V2)')),
'iBob' : np.array(raw.get_trace('I(L1)'))
}
except KeyError as e:
print(f'Error: {e}')
return None
if __name__ == '__main__':
lts_path = "C:/Users/osuescuneli/AppData/Local/Programs/ADI/LTspice/LTspice.exe"
Tension = 150
Resistencia = 1.942
Inductancia = 11e-6
Capacitancia = 1e-3
tiempoSimulacion = 0.02
tiempoSwitch = 1e-3
tiempoMos = 1.5e-3
resultado = simular(Tension,
Resistencia,
Inductancia,
Capacitancia,
lts_path,
tSim = tiempoSimulacion,
toff_sw = tiempoSwitch,
ton_mos = tiempoMos)
plt.figure()
plt.plot(resultado['tiempo'], resultado['vCap'], label='Tension Cap [V]')
plt.plot(resultado['tiempo'], resultado['vBob'], label='Tension Bobina [V]')
plt.plot(resultado['tiempo'], resultado['iBob'], label='Corriente Bobina [A]')
plt.grid()
plt.legend()
plt.show()

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[Transient Analysis]
{
Npanes: 2
Active Pane: 1
{
traces: 1 {589830,0,"V(V1,V2)*I(L1)"}
X: ('m',0,0,0.001,0.01)
Y[0]: ('K',1,-300,300,3000)
Y[1]: ('K',0,1e+308,1000,-1e+308)
Units: "W" ('K',0,0,1,-300,300,3000)
Log: 0 0 0
GridStyle: 1
},
{
traces: 2 {269025282,0,"V(n001)"} {303104004,1,"I(L1)"}
X: ('m',0,0,0.001,0.01)
Y[0]: (' ',0,-20,20,200)
Y[1]: (' ',0,-10,10,100)
Volts: (' ',0,0,0,-20,20,200)
Amps: (' ',0,0,0,-10,10,100)
Log: 0 0 0
GridStyle: 1
}
}

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Version 4.1 Version 4.1
SHEET 1 1192 852 SHEET 1 1192 852
WIRE 480 -176 432 -176
WIRE 544 -176 480 -176
WIRE 624 -176 544 -176
WIRE 544 -160 544 -176
WIRE 432 -144 432 -176
WIRE 624 -144 624 -176
WIRE 432 -64 432 -80
WIRE 544 -64 544 -80
WIRE 544 -64 432 -64
WIRE 624 -64 624 -80
WIRE 624 -64 544 -64
WIRE 432 -32 432 -64
WIRE -96 48 -256 48 WIRE -96 48 -256 48
WIRE 0 48 -96 48 WIRE 0 48 -96 48
WIRE 256 48 0 48 WIRE 256 48 0 48
@ -37,8 +25,6 @@ FLAG -256 336 0
FLAG 0 208 0 FLAG 0 208 0
FLAG 256 176 V1 FLAG 256 176 V1
FLAG 256 304 V2 FLAG 256 304 V2
FLAG 432 -32 0
FLAG 480 -176 Energia
FLAG -96 48 condensador FLAG -96 48 condensador
SYMBOL voltage -256 224 R0 SYMBOL voltage -256 224 R0
WINDOW 123 0 0 Left 0 WINDOW 123 0 0 Left 0
@ -73,24 +59,13 @@ SYMATTR Value {L}
SYMBOL res 240 64 R0 SYMBOL res 240 64 R0
SYMATTR InstName R1 SYMATTR InstName R1
SYMATTR Value {R} SYMATTR Value {R}
SYMBOL ltspice-lib\\sym\\bi 432 -64 R180 TEXT -320 -16 Left 2 !.tran 0 {tsim} 0
WINDOW 0 -54 81 Left 2
WINDOW 3 11 85 Left 2
SYMATTR InstName B1
SYMATTR Value I = (V(V1)-V(V2))*I(L1)
SYMBOL cap 608 -144 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 528 -176 R0
SYMATTR InstName R2
SYMATTR Value 100G
TEXT -320 -16 Left 2 !.tran 0 {tsim} 0 uic
TEXT -320 -48 Left 2 !.Model SW SW(Ron=1m Roff=100Meg Vt = 5) TEXT -320 -48 Left 2 !.Model SW SW(Ron=1m Roff=100Meg Vt = 5)
TEXT -320 -176 Left 2 !.param tsim 100m TEXT -320 -176 Left 2 !.param tsim 100m
TEXT -320 -144 Left 2 !.param toff_sw 1m TEXT -320 -144 Left 2 !.param toff_sw 1m
TEXT -320 -112 Left 2 !.param ton_mos 1.5m TEXT -320 -112 Left 2 !.param ton_mos 1.5m
TEXT -320 472 Left 2 !.param R 1.942 TEXT 336 -96 Left 2 !.param R 1.942
TEXT -320 408 Left 2 !.param C 1m TEXT 336 -160 Left 2 !.param C 1m
TEXT -320 440 Left 2 !.param L 11u TEXT 336 -128 Left 2 !.param L 11u
TEXT -320 504 Left 2 !.param V 150 TEXT 336 -64 Left 2 !.param V 150
TEXT -320 -80 Left 2 !.param delta tsim-ton_mos TEXT -320 -80 Left 2 !.param delta tsim-ton_mos

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* C:\Users\osuescuneli\Desktop\source\src\modelo_transitorio.asc * C:\Users\osuescuneli\Desktop\source\src\simulador\modelo_transitorio.asc
* Generated by LTspice 24.1.5 for Windows. * Generated by LTspice 24.1.5 for Windows.
V1 N001 0 {V} V1 N001 0 {V}
S1 N001 condensador cont1 0 SW S1 N001 condensador cont1 0 SW
@ -8,13 +8,10 @@ M1 V2 cont2 0 0 IRFZ44N
V3 cont2 0 PULSE(0 15 {ton_mos} 1n 1n {delta} {tsim}) V3 cont2 0 PULSE(0 15 {ton_mos} 1n 1n {delta} {tsim})
L1 V1 V2 {L} L1 V1 V2 {L}
R1 condensador V1 {R} R1 condensador V1 {R}
B1 0 Energia I = (V(V1)-V(V2))*I(L1)
C2 Energia 0 1
R2 Energia 0 100G
.model NMOS NMOS .model NMOS NMOS
.model PMOS PMOS .model PMOS PMOS
.lib C:\Users\osuescuneli\AppData\Local\LTspice\lib\cmp\standard.mos .lib C:\Users\osuescuneli\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 {tsim} 0 uic .tran 0 {tsim} 0
.Model SW SW(Ron=1m Roff=100Meg Vt = 5) .Model SW SW(Ron=1m Roff=100Meg Vt = 5)
.param tsim 100m .param tsim 100m
.param toff_sw 1m .param toff_sw 1m

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* C:\Users\osuescuneli\Desktop\source\src\simulador\modelo_transitorio.asc
* Generated by LTspice 24.1.5 for Windows.
V1 N001 0 {V}
S1 N001 condensador cont1 0 SW
V2 cont1 0 PULSE(0 10 0 1n 1n {toff_sw} {tsim})
C1 condensador 0 {C}
M1 V2 cont2 0 0 IRFZ44N
V3 cont2 0 PULSE(0 15 {ton_mos} 1n 1n {delta} {tsim})
L1 V1 V2 {L}
R1 condensador V1 {R}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\osuescuneli\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 {tsim} 0
.Model SW SW(Ron=1m Roff=100Meg Vt = 5)
.param tsim 20m
.param toff_sw 1m
.param ton_mos 1.5m
.param R 1.942
.param C 1m
.param L 11u
.param V 150
.param delta tsim-ton_mos
.backanno
.end

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