/*
 * speedgoat_test_SN10564_R2024a.cpp
 *
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * Code generation for model "speedgoat_test_SN10564_R2024a".
 *
 * Model version              : 1.3
 * Simulink Coder version : 24.1 (R2024a) 19-Nov-2023
 * C++ source code generated on : Thu Nov  7 11:28:20 2024
 *
 * Target selection: speedgoat.tlc
 * Note: GRT includes extra infrastructure and instrumentation for prototyping
 * Embedded hardware selection: Intel->x86-64 (Linux 64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#include "speedgoat_test_SN10564_R2024a.h"
#include "speedgoat_test_SN10564_R2024a_private.h"
#include "speedgoat_test_SN10564_R2024a_cal.h"
#include "rtwtypes.h"
#include "rte_speedgoat_test_SN10564_R2024a_parameters.h"
#include <cmath>
#include <cstring>

extern "C"
{

#include "rt_nonfinite.h"

}

/* Block signals (default storage) */
B_speedgoat_test_SN10564_R2024a_T speedgoat_test_SN10564_R2024a_B;

/* Block states (default storage) */
DW_speedgoat_test_SN10564_R2024a_T speedgoat_test_SN10564_R2024a_DW;

/* Real-time model */
RT_MODEL_speedgoat_test_SN10564_R2024a_T speedgoat_test_SN10564_R2024a_M_ =
  RT_MODEL_speedgoat_test_SN10564_R2024a_T();
RT_MODEL_speedgoat_test_SN10564_R2024a_T *const speedgoat_test_SN10564_R2024a_M =
  &speedgoat_test_SN10564_R2024a_M_;
void S4_InterruptSetup1_callback(void)
{
  // 2.  Call the framework to get the msg receive coid to use in the pulse send in the ISR
  S4_InterruptSetup1_D.coid = slrealtime::taskConnectionID( 1 );
  IO397_50k_start_public( S4_InterruptSetup1_D.context, 0 );
}

int32_T div_s32(int32_T numerator, int32_T denominator)
{
  int32_T quotient;
  if (denominator == 0) {
    quotient = numerator >= 0 ? MAX_int32_T : MIN_int32_T;

    /* Divide by zero handler */
  } else {
    uint32_T tempAbsQuotient;
    tempAbsQuotient = (numerator < 0 ? ~static_cast<uint32_T>(numerator) + 1U :
                       static_cast<uint32_T>(numerator)) / (denominator < 0 ? ~
      static_cast<uint32_T>(denominator) + 1U : static_cast<uint32_T>
      (denominator));
    quotient = (numerator < 0) != (denominator < 0) ? -static_cast<int32_T>
      (tempAbsQuotient) : static_cast<int32_T>(tempAbsQuotient);
  }

  return quotient;
}

const struct sigevent *S4_InterruptSetup1_ISR(void *data, int id)
{
  // For the real interrupt, call the boardISR here
  bool needService = IO397_50k_isr_public( S4_InterruptSetup1_D.context );
  if (needService ) {
    S4_InterruptSetup1_D.count++;

    // Call the INIT macro again to send the current count.
    SIGEV_PULSE_INT_INIT( &S4_InterruptSetup1_D.sig_pulse,
                         S4_InterruptSetup1_D.coid,
                         S4_InterruptSetup1_D.pri,
                         _PULSE_CODE_MINAVAIL,
                         S4_InterruptSetup1_D.count );
    return &S4_InterruptSetup1_D.sig_pulse;
  }

  // return a sigevent none if the board didn't interrupt.
  return &S4_InterruptSetup1_D.sig_none;
}

// SimulinkRealTime Target Async Interrupt Block '<S4>/Interrupt Setup 1'
// Same function for interrupt or polling mode.
void S4_InterruptSetup1_fc(void)
{
  {
    /* Reset subsysRan breadcrumbs */
    srClearBC(speedgoat_test_SN10564_R2024a_DW.FunctionCallSubsystem_SubsysRan);

    /* S-Function (slhwinterrupt): '<S4>/Interrupt Setup 1' */

    /* Output and update for function-call system: '<S4>/Function-Call Subsystem' */
    rtw_slrealtime_mutex_lock
      (speedgoat_test_SN10564_R2024a_M->Timing.semIdForTask1);
    speedgoat_test_SN10564_R2024a_M->Timing.clockTick1 =
      speedgoat_test_SN10564_R2024a_M->Timing.rtmClockTickBuf1;
    speedgoat_test_SN10564_R2024a_M->Timing.clockTickH1 =
      speedgoat_test_SN10564_R2024a_M->Timing.rtmBufClockTickBufH1;
    rtw_slrealtime_mutex_unlock
      (speedgoat_test_SN10564_R2024a_M->Timing.semIdForTask1);
    speedgoat_test_SN10564_R2024a_M->Timing.t[1] =
      speedgoat_test_SN10564_R2024a_M->Timing.clockTick1 *
      speedgoat_test_SN10564_R2024a_M->Timing.stepSize1 +
      speedgoat_test_SN10564_R2024a_M->Timing.clockTickH1 *
      speedgoat_test_SN10564_R2024a_M->Timing.stepSize1 * 4294967296.0;

    /* UnitDelay: '<S7>/Output' */
    speedgoat_test_SN10564_R2024a_B.Output =
      speedgoat_test_SN10564_R2024a_DW.Output_DSTATE;

    /* Sum: '<S8>/FixPt Sum1' incorporates:
     *  Constant: '<S8>/FixPt Constant'
     */
    speedgoat_test_SN10564_R2024a_B.FixPtSum1 =
      speedgoat_test_SN10564_R2024a_B.Output +
      speedgoat_test_SN10564_R202_cal->FixPtConstant_Value;

    /* Switch: '<S9>/FixPt Switch' */
    if (speedgoat_test_SN10564_R2024a_B.FixPtSum1 >
        speedgoat_test_SN10564_R202_cal->WrapToZero_Threshold) {
      /* Switch: '<S9>/FixPt Switch' incorporates:
       *  Constant: '<S9>/Constant'
       */
      speedgoat_test_SN10564_R2024a_B.FixPtSwitch =
        speedgoat_test_SN10564_R202_cal->Constant_Value;
    } else {
      /* Switch: '<S9>/FixPt Switch' */
      speedgoat_test_SN10564_R2024a_B.FixPtSwitch =
        speedgoat_test_SN10564_R2024a_B.FixPtSum1;
    }

    /* End of Switch: '<S9>/FixPt Switch' */

    /* S-Function (sg_fpga_inta_sf_a1): '<S6>/CoS Interrupt' */

    /* Level2 S-Function Block: '<S6>/CoS Interrupt' (sg_fpga_inta_sf_a1) */
    {
      SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[0];
      sfcnOutputs(rts,1);
    }

    /* Update for UnitDelay: '<S7>/Output' */
    speedgoat_test_SN10564_R2024a_DW.Output_DSTATE =
      speedgoat_test_SN10564_R2024a_B.FixPtSwitch;
    speedgoat_test_SN10564_R2024a_DW.FunctionCallSubsystem_SubsysRan = 4;

    /* End of Outputs for S-Function (slhwinterrupt): '<S4>/Interrupt Setup 1' */
  }
}

/* Model step function */
void speedgoat_test_SN10564_R2024a_step(void)
{
  real_T HoldCosine;
  real_T HoldSine;
  int32_T clockTickCounter;
  int32_T i;

  /* Sin: '<S5>/Sine Wave' */
  HoldCosine = *get_Ts();

  /* S-Function (sg_fpga_di_sf_a2): '<S3>/Digital input' */

  /* Level2 S-Function Block: '<S3>/Digital input' (sg_fpga_di_sf_a2) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[1];
    sfcnOutputs(rts,0);
  }

  for (i = 0; i < 5; i++) {
    /* Bias: '<S3>/Offset' */
    speedgoat_test_SN10564_R2024a_B.IO397DI[i] =
      speedgoat_test_SN10564_R2024a_B.Digitalinput[i] +
      speedgoat_test_SN10564_R202_cal->Offset_Bias[i];
  }

  for (i = 0; i < 6; i++) {
    /* DiscretePulseGenerator: '<S3>/Pulse Gen DIO' */
    clockTickCounter = speedgoat_test_SN10564_R2024a_DW.clockTickCounter[i];

    /* DiscretePulseGenerator: '<S3>/Pulse Gen DIO' */
    speedgoat_test_SN10564_R2024a_B.PulseGenDIO[i] = (clockTickCounter <
      speedgoat_test_SN10564_R202_cal->PulseGenDIO_Duty) && (clockTickCounter >=
      0) ? speedgoat_test_SN10564_R202_cal->PulseGenDIO_Amp : 0.0;

    /* DiscretePulseGenerator: '<S3>/Pulse Gen DIO' */
    if (clockTickCounter >= speedgoat_test_SN10564_R202_cal->PulseGenDIO_Period
        - 1.0) {
      clockTickCounter = 0;
    } else {
      clockTickCounter++;
    }

    speedgoat_test_SN10564_R2024a_DW.clockTickCounter[i] = clockTickCounter;
  }

  /* S-Function (sg_fpga_do_sf_a2): '<S3>/Digital output' */

  /* Level2 S-Function Block: '<S3>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[2];
    sfcnOutputs(rts,0);
  }

  /* RateTransition: '<S4>/Rate Transition' */
  speedgoat_test_SN10564_R2024a_B.IO3xx_Interrupt =
    speedgoat_test_SN10564_R2024a_B.Output;

  /* S-Function (sg_fpga_IO397_ad): '<S5>/IO397 Analog Input' */

  /* Level2 S-Function Block: '<S5>/IO397 Analog Input' (sg_fpga_IO397_ad) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[3];
    sfcnOutputs(rts,0);
  }

  /* Gain: '<S5>/Gain1' */
  speedgoat_test_SN10564_R2024a_B.IO397_AI_CH01 =
    speedgoat_test_SN10564_R202_cal->Gain1_Gain *
    speedgoat_test_SN10564_R2024a_B.IO397AnalogInput_o1;

  /* Gain: '<S5>/Gain2' */
  speedgoat_test_SN10564_R2024a_B.IO397_AI_CH02 =
    speedgoat_test_SN10564_R202_cal->Gain2_Gain *
    speedgoat_test_SN10564_R2024a_B.IO397AnalogInput_o2;

  /* Gain: '<S5>/Gain3' */
  speedgoat_test_SN10564_R2024a_B.IO397_AI_CH03 =
    speedgoat_test_SN10564_R202_cal->Gain3_Gain *
    speedgoat_test_SN10564_R2024a_B.IO397AnalogInput_o3;

  /* Gain: '<S5>/Gain4' */
  speedgoat_test_SN10564_R2024a_B.IO397_AI_CH04 =
    speedgoat_test_SN10564_R202_cal->Gain4_Gain *
    speedgoat_test_SN10564_R2024a_B.IO397AnalogInput_o4;

  /* Sin: '<S5>/Sine Wave' */
  if (speedgoat_test_SN10564_R2024a_DW.systemEnable != 0) {
    HoldSine = 1.0 / HoldCosine * 6.2831853071795862 / 50.0;
    speedgoat_test_SN10564_R2024a_DW.lastSin = std::sin(HoldSine *
      speedgoat_test_SN10564_R2024a_M->Timing.t[0]);
    HoldSine = 1.0 / HoldCosine * 6.2831853071795862 / 50.0;
    speedgoat_test_SN10564_R2024a_DW.lastCos = std::cos(HoldSine *
      speedgoat_test_SN10564_R2024a_M->Timing.t[0]);
    speedgoat_test_SN10564_R2024a_DW.systemEnable = 0;
  }

  /* Sin: '<S5>/Sine Wave' */
  speedgoat_test_SN10564_R2024a_B.SineWave =
    ((speedgoat_test_SN10564_R2024a_DW.lastSin *
      speedgoat_test_SN10564_R202_cal->SineWave_PCos +
      speedgoat_test_SN10564_R2024a_DW.lastCos *
      speedgoat_test_SN10564_R202_cal->SineWave_PSin) *
     speedgoat_test_SN10564_R202_cal->SineWave_HCos +
     (speedgoat_test_SN10564_R2024a_DW.lastCos *
      speedgoat_test_SN10564_R202_cal->SineWave_PCos -
      speedgoat_test_SN10564_R2024a_DW.lastSin *
      speedgoat_test_SN10564_R202_cal->SineWave_PSin) *
     speedgoat_test_SN10564_R202_cal->SineWave_Hsin) *
    speedgoat_test_SN10564_R202_cal->SineWave_Amp +
    speedgoat_test_SN10564_R202_cal->SineWave_Bias;

  /* S-Function (sg_fpga_IO397_da): '<S5>/IO397 Analog Output' */

  /* Level2 S-Function Block: '<S5>/IO397 Analog Output' (sg_fpga_IO397_da) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[4];
    sfcnOutputs(rts,0);
  }

  /* user code (Output function Trailer for TID0) */
  {
    if (0) {
      io3xx_sgdma_feedSequential(1);
    }
  }

  /* Update for Sin: '<S5>/Sine Wave' */
  HoldSine = speedgoat_test_SN10564_R2024a_DW.lastSin;
  HoldCosine = speedgoat_test_SN10564_R2024a_DW.lastCos;
  speedgoat_test_SN10564_R2024a_DW.lastSin = HoldSine *
    speedgoat_test_SN10564_R202_cal->SineWave_HCos + HoldCosine *
    speedgoat_test_SN10564_R202_cal->SineWave_Hsin;
  speedgoat_test_SN10564_R2024a_DW.lastCos = HoldCosine *
    speedgoat_test_SN10564_R202_cal->SineWave_HCos - HoldSine *
    speedgoat_test_SN10564_R202_cal->SineWave_Hsin;

  /* Update absolute time for base rate */
  /* The "clockTick0" counts the number of times the code of this task has
   * been executed. The absolute time is the multiplication of "clockTick0"
   * and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
   * overflow during the application lifespan selected.
   * Timer of this task consists of two 32 bit unsigned integers.
   * The two integers represent the low bits Timing.clockTick0 and the high bits
   * Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
   */
  if (!(++speedgoat_test_SN10564_R2024a_M->Timing.clockTick0)) {
    ++speedgoat_test_SN10564_R2024a_M->Timing.clockTickH0;
  }

  speedgoat_test_SN10564_R2024a_M->Timing.t[0] =
    speedgoat_test_SN10564_R2024a_M->Timing.clockTick0 *
    speedgoat_test_SN10564_R2024a_M->Timing.stepSize0 +
    speedgoat_test_SN10564_R2024a_M->Timing.clockTickH0 *
    speedgoat_test_SN10564_R2024a_M->Timing.stepSize0 * 4294967296.0;
  rtw_slrealtime_mutex_lock
    (speedgoat_test_SN10564_R2024a_M->Timing.semIdForTask1);
  speedgoat_test_SN10564_R2024a_M->Timing.rtmClockTickBuf1 =
    speedgoat_test_SN10564_R2024a_M->Timing.clockTick0;
  speedgoat_test_SN10564_R2024a_M->Timing.rtmBufClockTickBufH1 =
    speedgoat_test_SN10564_R2024a_M->Timing.clockTickH0;
  rtw_slrealtime_mutex_unlock
    (speedgoat_test_SN10564_R2024a_M->Timing.semIdForTask1);
}

/* Model initialize function */
void speedgoat_test_SN10564_R2024a_initialize(void)
{
  /* Registration code */

  /* initialize non-finites */
  rt_InitInfAndNaN(sizeof(real_T));
  rtsiSetSolverName(&speedgoat_test_SN10564_R2024a_M->solverInfo,
                    "FixedStepDiscrete");
  speedgoat_test_SN10564_R2024a_M->solverInfoPtr =
    (&speedgoat_test_SN10564_R2024a_M->solverInfo);

  /* Initialize timing info */
  {
    int_T *mdlTsMap =
      speedgoat_test_SN10564_R2024a_M->Timing.sampleTimeTaskIDArray;
    mdlTsMap[0] = 0;

    /* polyspace +2 MISRA2012:D4.1 [Justified:Low] "speedgoat_test_SN10564_R2024a_M points to
       static memory which is guaranteed to be non-NULL" */
    speedgoat_test_SN10564_R2024a_M->Timing.sampleTimeTaskIDPtr = (&mdlTsMap[0]);
    speedgoat_test_SN10564_R2024a_M->Timing.sampleTimes =
      (&speedgoat_test_SN10564_R2024a_M->Timing.sampleTimesArray[0]);
    speedgoat_test_SN10564_R2024a_M->Timing.offsetTimes =
      (&speedgoat_test_SN10564_R2024a_M->Timing.offsetTimesArray[0]);

    /* task periods */
    speedgoat_test_SN10564_R2024a_M->Timing.sampleTimes[0] = (0.001);

    /* task offsets */
    speedgoat_test_SN10564_R2024a_M->Timing.offsetTimes[0] = (0.0);
  }

  rtmSetTPtr(speedgoat_test_SN10564_R2024a_M,
             &speedgoat_test_SN10564_R2024a_M->Timing.tArray[0]);

  {
    int_T *mdlSampleHits =
      speedgoat_test_SN10564_R2024a_M->Timing.sampleHitArray;
    mdlSampleHits[0] = 1;
    speedgoat_test_SN10564_R2024a_M->Timing.sampleHits = (&mdlSampleHits[0]);
  }

  rtmSetTFinal(speedgoat_test_SN10564_R2024a_M, -1);
  speedgoat_test_SN10564_R2024a_M->Timing.stepSize0 = 0.001;
  speedgoat_test_SN10564_R2024a_M->Timing.stepSize1 = 0.001;
  speedgoat_test_SN10564_R2024a_M->solverInfoPtr =
    (&speedgoat_test_SN10564_R2024a_M->solverInfo);
  speedgoat_test_SN10564_R2024a_M->Timing.stepSize = (0.001);
  rtsiSetFixedStepSize(&speedgoat_test_SN10564_R2024a_M->solverInfo, 0.001);
  rtsiSetSolverMode(&speedgoat_test_SN10564_R2024a_M->solverInfo,
                    SOLVER_MODE_SINGLETASKING);

  /* block I/O */
  (void) std::memset((static_cast<void *>(&speedgoat_test_SN10564_R2024a_B)), 0,
                     sizeof(B_speedgoat_test_SN10564_R2024a_T));

  /* states (dwork) */
  (void) std::memset(static_cast<void *>(&speedgoat_test_SN10564_R2024a_DW), 0,
                     sizeof(DW_speedgoat_test_SN10564_R2024a_T));

  /* child S-Function registration */
  {
    RTWSfcnInfo *sfcnInfo =
      &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.sfcnInfo;
    speedgoat_test_SN10564_R2024a_M->sfcnInfo = (sfcnInfo);
    rtssSetErrorStatusPtr(sfcnInfo, (&rtmGetErrorStatus
      (speedgoat_test_SN10564_R2024a_M)));
    speedgoat_test_SN10564_R2024a_M->Sizes.numSampTimes = (2);
    rtssSetNumRootSampTimesPtr(sfcnInfo,
      &speedgoat_test_SN10564_R2024a_M->Sizes.numSampTimes);
    speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.taskTimePtrs[0] =
      (&rtmGetTPtr(speedgoat_test_SN10564_R2024a_M)[0]);
    speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.taskTimePtrs[1] =
      (&rtmGetTPtr(speedgoat_test_SN10564_R2024a_M)[1]);
    rtssSetTPtrPtr(sfcnInfo,
                   speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.taskTimePtrs);
    rtssSetTStartPtr(sfcnInfo, &rtmGetTStart(speedgoat_test_SN10564_R2024a_M));
    rtssSetTFinalPtr(sfcnInfo, &rtmGetTFinal(speedgoat_test_SN10564_R2024a_M));
    rtssSetTimeOfLastOutputPtr(sfcnInfo, &rtmGetTimeOfLastOutput
      (speedgoat_test_SN10564_R2024a_M));
    rtssSetStepSizePtr(sfcnInfo,
                       &speedgoat_test_SN10564_R2024a_M->Timing.stepSize);
    rtssSetStopRequestedPtr(sfcnInfo, &rtmGetStopRequested
      (speedgoat_test_SN10564_R2024a_M));
    rtssSetDerivCacheNeedsResetPtr(sfcnInfo,
      &speedgoat_test_SN10564_R2024a_M->derivCacheNeedsReset);
    rtssSetZCCacheNeedsResetPtr(sfcnInfo,
      &speedgoat_test_SN10564_R2024a_M->zCCacheNeedsReset);
    rtssSetContTimeOutputInconsistentWithStateAtMajorStepPtr(sfcnInfo,
      &speedgoat_test_SN10564_R2024a_M->CTOutputIncnstWithState);
    rtssSetSampleHitsPtr(sfcnInfo,
                         &speedgoat_test_SN10564_R2024a_M->Timing.sampleHits);
    rtssSetPerTaskSampleHitsPtr(sfcnInfo,
      &speedgoat_test_SN10564_R2024a_M->Timing.perTaskSampleHits);
    rtssSetSimModePtr(sfcnInfo, &speedgoat_test_SN10564_R2024a_M->simMode);
    rtssSetSolverInfoPtr(sfcnInfo,
                         &speedgoat_test_SN10564_R2024a_M->solverInfoPtr);
  }

  speedgoat_test_SN10564_R2024a_M->Sizes.numSFcns = (5);

  /* register each child */
  {
    (void) std::memset(static_cast<void *>
                       (&speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.childSFunctions
                        [0]), 0,
                       5*sizeof(SimStruct));
    speedgoat_test_SN10564_R2024a_M->childSfunctions =
      (&speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.childSFunctionPtrs[0]);

    {
      int_T i;
      for (i = 0; i < 5; i++) {
        speedgoat_test_SN10564_R2024a_M->childSfunctions[i] =
          (&speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.childSFunctions[i]);
      }
    }

    /* Level2 S-Function Block: speedgoat_test_SN10564_R2024a/<S6>/CoS Interrupt (sg_fpga_inta_sf_a1) */
    {
      SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[0];

      /* timing info */
      time_T *sfcnPeriod =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn0.sfcnPeriod;
      time_T *sfcnOffset =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn0.sfcnOffset;
      int_T *sfcnTsMap =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn0.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.blkInfo2
                         [0]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.inputOutputPortInfo2[0]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, speedgoat_test_SN10564_R2024a_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods2
                           [0]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods3
                           [0]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods4
                           [0]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.statesInfo2
                         [0]);
        ssSetPeriodicStatesInfo(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.periodicStatesInfo[0]);
      }

      /* path info */
      ssSetModelName(rts, "CoS Interrupt");
      ssSetPath(rts,
                "speedgoat_test_SN10564_R2024a/IO397-50k/INTA/Function-Call Subsystem/CoS Interrupt");
      ssSetRTModel(rts,speedgoat_test_SN10564_R2024a_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn0.params;
        ssSetSFcnParamsCount(rts, 5);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->CoSInterrupt_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->CoSInterrupt_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->CoSInterrupt_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->CoSInterrupt_P4_Size);
        ssSetSFcnParam(rts, 4, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->CoSInterrupt_P5_Size);
      }

      /* work vectors */
      ssSetRWork(rts, (real_T *)
                 &speedgoat_test_SN10564_R2024a_DW.CoSInterrupt_RWORK[0]);
      ssSetIWork(rts, (int_T *)
                 &speedgoat_test_SN10564_R2024a_DW.CoSInterrupt_IWORK);
      ssSetPWork(rts, (void **)
                 &speedgoat_test_SN10564_R2024a_DW.CoSInterrupt_PWORK);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn0.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn0.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 3);

        /* RWORK */
        ssSetDWorkWidthAsInt(rts, 0, 16);
        ssSetDWorkDataType(rts, 0,SS_DOUBLE);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0, &speedgoat_test_SN10564_R2024a_DW.CoSInterrupt_RWORK
                   [0]);

        /* IWORK */
        ssSetDWorkWidthAsInt(rts, 1, 1);
        ssSetDWorkDataType(rts, 1,SS_INTEGER);
        ssSetDWorkComplexSignal(rts, 1, 0);
        ssSetDWork(rts, 1, &speedgoat_test_SN10564_R2024a_DW.CoSInterrupt_IWORK);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 2, 1);
        ssSetDWorkDataType(rts, 2,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 2, 0);
        ssSetDWork(rts, 2, &speedgoat_test_SN10564_R2024a_DW.CoSInterrupt_PWORK);
      }

      /* registration */
      sg_fpga_inta_sf_a1(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, -1.0);
      ssSetOffsetTime(rts, 0, -2.0);
      sfcnTsMap[0] = 1;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      /* Update the BufferDstPort flags for each input port */
    }

    /* Level2 S-Function Block: speedgoat_test_SN10564_R2024a/<S3>/Digital input (sg_fpga_di_sf_a2) */
    {
      SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[1];

      /* timing info */
      time_T *sfcnPeriod =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn1.sfcnPeriod;
      time_T *sfcnOffset =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn1.sfcnOffset;
      int_T *sfcnTsMap =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn1.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.blkInfo2
                         [1]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.inputOutputPortInfo2[1]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, speedgoat_test_SN10564_R2024a_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods2
                           [1]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods3
                           [1]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods4
                           [1]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.statesInfo2
                         [1]);
        ssSetPeriodicStatesInfo(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.periodicStatesInfo[1]);
      }

      /* outputs */
      {
        ssSetPortInfoForOutputs(rts,
          &speedgoat_test_SN10564_R2024a_M->
          NonInlinedSFcns.Sfcn1.outputPortInfo[0]);
        ssSetPortInfoForOutputs(rts,
          &speedgoat_test_SN10564_R2024a_M->
          NonInlinedSFcns.Sfcn1.outputPortInfo[0]);
        _ssSetNumOutputPorts(rts, 1);
        _ssSetPortInfo2ForOutputUnits(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn1.outputPortUnits
          [0]);
        ssSetOutputPortUnit(rts, 0, 0);
        _ssSetPortInfo2ForOutputCoSimAttribute(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn1.outputPortCoSimAttribute
          [0]);
        ssSetOutputPortIsContinuousQuantity(rts, 0, 0);

        /* port 0 */
        {
          _ssSetOutputPortNumDimensions(rts, 0, 1);
          ssSetOutputPortWidthAsInt(rts, 0, 5);
          ssSetOutputPortSignal(rts, 0, ((real_T *)
            speedgoat_test_SN10564_R2024a_B.Digitalinput));
        }
      }

      /* path info */
      ssSetModelName(rts, "Digital input");
      ssSetPath(rts, "speedgoat_test_SN10564_R2024a/IO397-50k/DIO/Digital input");
      ssSetRTModel(rts,speedgoat_test_SN10564_R2024a_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn1.params;
        ssSetSFcnParamsCount(rts, 4);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitalinput_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitalinput_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitalinput_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitalinput_P4_Size);
      }

      /* work vectors */
      ssSetPWork(rts, (void **)
                 &speedgoat_test_SN10564_R2024a_DW.Digitalinput_PWORK[0]);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn1.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn1.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 1);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 0, 2);
        ssSetDWorkDataType(rts, 0,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0, &speedgoat_test_SN10564_R2024a_DW.Digitalinput_PWORK
                   [0]);
      }

      /* registration */
      sg_fpga_di_sf_a2(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, 0.001);
      ssSetOffsetTime(rts, 0, 0.0);
      sfcnTsMap[0] = 0;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      _ssSetOutputPortConnected(rts, 0, 1);
      _ssSetOutputPortBeingMerged(rts, 0, 0);

      /* Update the BufferDstPort flags for each input port */
    }

    /* Level2 S-Function Block: speedgoat_test_SN10564_R2024a/<S3>/Digital output (sg_fpga_do_sf_a2) */
    {
      SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[2];

      /* timing info */
      time_T *sfcnPeriod =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.sfcnPeriod;
      time_T *sfcnOffset =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.sfcnOffset;
      int_T *sfcnTsMap =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.blkInfo2
                         [2]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.inputOutputPortInfo2[2]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, speedgoat_test_SN10564_R2024a_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods2
                           [2]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods3
                           [2]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods4
                           [2]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.statesInfo2
                         [2]);
        ssSetPeriodicStatesInfo(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.periodicStatesInfo[2]);
      }

      /* inputs */
      {
        _ssSetNumInputPorts(rts, 1);
        ssSetPortInfoForInputs(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.inputPortInfo
          [0]);
        ssSetPortInfoForInputs(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.inputPortInfo
          [0]);
        _ssSetPortInfo2ForInputUnits(rts,
          &speedgoat_test_SN10564_R2024a_M->
          NonInlinedSFcns.Sfcn2.inputPortUnits[0]);
        ssSetInputPortUnit(rts, 0, 0);
        _ssSetPortInfo2ForInputCoSimAttribute(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.inputPortCoSimAttribute
          [0]);
        ssSetInputPortIsContinuousQuantity(rts, 0, 0);

        /* port 0 */
        {
          ssSetInputPortRequiredContiguous(rts, 0, 1);
          ssSetInputPortSignal(rts, 0,
                               speedgoat_test_SN10564_R2024a_B.PulseGenDIO);
          _ssSetInputPortNumDimensions(rts, 0, 1);
          ssSetInputPortWidthAsInt(rts, 0, 6);
        }
      }

      /* path info */
      ssSetModelName(rts, "Digital output");
      ssSetPath(rts,
                "speedgoat_test_SN10564_R2024a/IO397-50k/DIO/Digital output");
      ssSetRTModel(rts,speedgoat_test_SN10564_R2024a_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.params;
        ssSetSFcnParamsCount(rts, 6);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitaloutput_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitaloutput_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitaloutput_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitaloutput_P4_Size);
        ssSetSFcnParam(rts, 4, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitaloutput_P5_Size);
        ssSetSFcnParam(rts, 5, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->Digitaloutput_P6_Size);
      }

      /* work vectors */
      ssSetPWork(rts, (void **)
                 &speedgoat_test_SN10564_R2024a_DW.Digitaloutput_PWORK[0]);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn2.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 1);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 0, 2);
        ssSetDWorkDataType(rts, 0,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0,
                   &speedgoat_test_SN10564_R2024a_DW.Digitaloutput_PWORK[0]);
      }

      /* registration */
      sg_fpga_do_sf_a2(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, 0.001);
      ssSetOffsetTime(rts, 0, 0.0);
      sfcnTsMap[0] = 0;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      _ssSetInputPortConnected(rts, 0, 1);

      /* Update the BufferDstPort flags for each input port */
      ssSetInputPortBufferDstPort(rts, 0, -1);
    }

    /* Level2 S-Function Block: speedgoat_test_SN10564_R2024a/<S5>/IO397 Analog Input (sg_fpga_IO397_ad) */
    {
      SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[3];

      /* timing info */
      time_T *sfcnPeriod =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn3.sfcnPeriod;
      time_T *sfcnOffset =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn3.sfcnOffset;
      int_T *sfcnTsMap =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn3.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.blkInfo2
                         [3]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.inputOutputPortInfo2[3]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, speedgoat_test_SN10564_R2024a_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods2
                           [3]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods3
                           [3]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods4
                           [3]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.statesInfo2
                         [3]);
        ssSetPeriodicStatesInfo(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.periodicStatesInfo[3]);
      }

      /* outputs */
      {
        ssSetPortInfoForOutputs(rts,
          &speedgoat_test_SN10564_R2024a_M->
          NonInlinedSFcns.Sfcn3.outputPortInfo[0]);
        ssSetPortInfoForOutputs(rts,
          &speedgoat_test_SN10564_R2024a_M->
          NonInlinedSFcns.Sfcn3.outputPortInfo[0]);
        _ssSetNumOutputPorts(rts, 4);
        _ssSetPortInfo2ForOutputUnits(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn3.outputPortUnits
          [0]);
        ssSetOutputPortUnit(rts, 0, 0);
        ssSetOutputPortUnit(rts, 1, 0);
        ssSetOutputPortUnit(rts, 2, 0);
        ssSetOutputPortUnit(rts, 3, 0);
        _ssSetPortInfo2ForOutputCoSimAttribute(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn3.outputPortCoSimAttribute
          [0]);
        ssSetOutputPortIsContinuousQuantity(rts, 0, 0);
        ssSetOutputPortIsContinuousQuantity(rts, 1, 0);
        ssSetOutputPortIsContinuousQuantity(rts, 2, 0);
        ssSetOutputPortIsContinuousQuantity(rts, 3, 0);

        /* port 0 */
        {
          _ssSetOutputPortNumDimensions(rts, 0, 1);
          ssSetOutputPortWidthAsInt(rts, 0, 1);
          ssSetOutputPortSignal(rts, 0, ((real_T *)
            &speedgoat_test_SN10564_R2024a_B.IO397AnalogInput_o1));
        }

        /* port 1 */
        {
          _ssSetOutputPortNumDimensions(rts, 1, 1);
          ssSetOutputPortWidthAsInt(rts, 1, 1);
          ssSetOutputPortSignal(rts, 1, ((real_T *)
            &speedgoat_test_SN10564_R2024a_B.IO397AnalogInput_o2));
        }

        /* port 2 */
        {
          _ssSetOutputPortNumDimensions(rts, 2, 1);
          ssSetOutputPortWidthAsInt(rts, 2, 1);
          ssSetOutputPortSignal(rts, 2, ((real_T *)
            &speedgoat_test_SN10564_R2024a_B.IO397AnalogInput_o3));
        }

        /* port 3 */
        {
          _ssSetOutputPortNumDimensions(rts, 3, 1);
          ssSetOutputPortWidthAsInt(rts, 3, 1);
          ssSetOutputPortSignal(rts, 3, ((real_T *)
            &speedgoat_test_SN10564_R2024a_B.IO397AnalogInput_o4));
        }
      }

      /* path info */
      ssSetModelName(rts, "IO397 Analog Input");
      ssSetPath(rts,
                "speedgoat_test_SN10564_R2024a/IO397-50k/IO39x_AD_DA/IO397 Analog Input");
      ssSetRTModel(rts,speedgoat_test_SN10564_R2024a_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn3.params;
        ssSetSFcnParamsCount(rts, 9);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P4_Size);
        ssSetSFcnParam(rts, 4, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P5_Size);
        ssSetSFcnParam(rts, 5, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P6_Size);
        ssSetSFcnParam(rts, 6, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P7_Size);
        ssSetSFcnParam(rts, 7, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P8_Size);
        ssSetSFcnParam(rts, 8, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogInput_P9_Size);
      }

      /* work vectors */
      ssSetPWork(rts, (void **)
                 &speedgoat_test_SN10564_R2024a_DW.IO397AnalogInput_PWORK[0]);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn3.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn3.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 1);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 0, 3);
        ssSetDWorkDataType(rts, 0,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0,
                   &speedgoat_test_SN10564_R2024a_DW.IO397AnalogInput_PWORK[0]);
      }

      /* registration */
      sg_fpga_IO397_ad(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, 0.001);
      ssSetOffsetTime(rts, 0, 0.0);
      sfcnTsMap[0] = 0;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      _ssSetOutputPortConnected(rts, 0, 1);
      _ssSetOutputPortConnected(rts, 1, 1);
      _ssSetOutputPortConnected(rts, 2, 1);
      _ssSetOutputPortConnected(rts, 3, 1);
      _ssSetOutputPortBeingMerged(rts, 0, 0);
      _ssSetOutputPortBeingMerged(rts, 1, 0);
      _ssSetOutputPortBeingMerged(rts, 2, 0);
      _ssSetOutputPortBeingMerged(rts, 3, 0);

      /* Update the BufferDstPort flags for each input port */
    }

    /* Level2 S-Function Block: speedgoat_test_SN10564_R2024a/<S5>/IO397 Analog Output (sg_fpga_IO397_da) */
    {
      SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[4];

      /* timing info */
      time_T *sfcnPeriod =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.sfcnPeriod;
      time_T *sfcnOffset =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.sfcnOffset;
      int_T *sfcnTsMap =
        speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.blkInfo2
                         [4]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.inputOutputPortInfo2[4]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, speedgoat_test_SN10564_R2024a_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods2
                           [4]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods3
                           [4]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts,
                           &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.methods4
                           [4]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts,
                         &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.statesInfo2
                         [4]);
        ssSetPeriodicStatesInfo(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.periodicStatesInfo[4]);
      }

      /* inputs */
      {
        _ssSetNumInputPorts(rts, 4);
        ssSetPortInfoForInputs(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.inputPortInfo
          [0]);
        ssSetPortInfoForInputs(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.inputPortInfo
          [0]);
        _ssSetPortInfo2ForInputUnits(rts,
          &speedgoat_test_SN10564_R2024a_M->
          NonInlinedSFcns.Sfcn4.inputPortUnits[0]);
        ssSetInputPortUnit(rts, 0, 0);
        ssSetInputPortUnit(rts, 1, 0);
        ssSetInputPortUnit(rts, 2, 0);
        ssSetInputPortUnit(rts, 3, 0);
        _ssSetPortInfo2ForInputCoSimAttribute(rts,
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.inputPortCoSimAttribute
          [0]);
        ssSetInputPortIsContinuousQuantity(rts, 0, 0);
        ssSetInputPortIsContinuousQuantity(rts, 1, 0);
        ssSetInputPortIsContinuousQuantity(rts, 2, 0);
        ssSetInputPortIsContinuousQuantity(rts, 3, 0);

        /* port 0 */
        {
          ssSetInputPortRequiredContiguous(rts, 0, 1);
          ssSetInputPortSignal(rts, 0, &speedgoat_test_SN10564_R2024a_B.SineWave);
          _ssSetInputPortNumDimensions(rts, 0, 1);
          ssSetInputPortWidthAsInt(rts, 0, 1);
        }

        /* port 1 */
        {
          ssSetInputPortRequiredContiguous(rts, 1, 1);
          ssSetInputPortSignal(rts, 1, &speedgoat_test_SN10564_R2024a_B.SineWave);
          _ssSetInputPortNumDimensions(rts, 1, 1);
          ssSetInputPortWidthAsInt(rts, 1, 1);
        }

        /* port 2 */
        {
          ssSetInputPortRequiredContiguous(rts, 2, 1);
          ssSetInputPortSignal(rts, 2, &speedgoat_test_SN10564_R2024a_B.SineWave);
          _ssSetInputPortNumDimensions(rts, 2, 1);
          ssSetInputPortWidthAsInt(rts, 2, 1);
        }

        /* port 3 */
        {
          ssSetInputPortRequiredContiguous(rts, 3, 1);
          ssSetInputPortSignal(rts, 3, &speedgoat_test_SN10564_R2024a_B.SineWave);
          _ssSetInputPortNumDimensions(rts, 3, 1);
          ssSetInputPortWidthAsInt(rts, 3, 1);
        }
      }

      /* path info */
      ssSetModelName(rts, "IO397 Analog Output");
      ssSetPath(rts,
                "speedgoat_test_SN10564_R2024a/IO397-50k/IO39x_AD_DA/IO397 Analog Output");
      ssSetRTModel(rts,speedgoat_test_SN10564_R2024a_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.params;
        ssSetSFcnParamsCount(rts, 6);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogOutput_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogOutput_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogOutput_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogOutput_P4_Size);
        ssSetSFcnParam(rts, 4, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogOutput_P5_Size);
        ssSetSFcnParam(rts, 5, (mxArray*)
                       speedgoat_test_SN10564_R202_cal->IO397AnalogOutput_P6_Size);
      }

      /* work vectors */
      ssSetIWork(rts, (int_T *)
                 &speedgoat_test_SN10564_R2024a_DW.IO397AnalogOutput_IWORK);
      ssSetPWork(rts, (void **)
                 &speedgoat_test_SN10564_R2024a_DW.IO397AnalogOutput_PWORK[0]);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &speedgoat_test_SN10564_R2024a_M->NonInlinedSFcns.Sfcn4.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 2);

        /* IWORK */
        ssSetDWorkWidthAsInt(rts, 0, 1);
        ssSetDWorkDataType(rts, 0,SS_INTEGER);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0,
                   &speedgoat_test_SN10564_R2024a_DW.IO397AnalogOutput_IWORK);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 1, 2);
        ssSetDWorkDataType(rts, 1,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 1, 0);
        ssSetDWork(rts, 1,
                   &speedgoat_test_SN10564_R2024a_DW.IO397AnalogOutput_PWORK[0]);
      }

      /* registration */
      sg_fpga_IO397_da(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, 0.001);
      ssSetOffsetTime(rts, 0, 0.0);
      sfcnTsMap[0] = 0;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      _ssSetInputPortConnected(rts, 0, 1);
      _ssSetInputPortConnected(rts, 1, 1);
      _ssSetInputPortConnected(rts, 2, 1);
      _ssSetInputPortConnected(rts, 3, 1);

      /* Update the BufferDstPort flags for each input port */
      ssSetInputPortBufferDstPort(rts, 0, -1);
      ssSetInputPortBufferDstPort(rts, 1, -1);
      ssSetInputPortBufferDstPort(rts, 2, -1);
      ssSetInputPortBufferDstPort(rts, 3, -1);
    }
  }

  /* Start for S-Function (sg_fpga_di_sf_a2): '<S3>/Digital input' */
  /* Level2 S-Function Block: '<S3>/Digital input' (sg_fpga_di_sf_a2) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[1];
    sfcnStart(rts);
    if (ssGetErrorStatus(rts) != (NULL))
      return;
  }

  /* Start for S-Function (sg_fpga_do_sf_a2): '<S3>/Digital output' */
  /* Level2 S-Function Block: '<S3>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[2];
    sfcnStart(rts);
    if (ssGetErrorStatus(rts) != (NULL))
      return;
  }

  /* Start for S-Function (sg_fpga_IO397_ad): '<S5>/IO397 Analog Input' */
  /* Level2 S-Function Block: '<S5>/IO397 Analog Input' (sg_fpga_IO397_ad) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[3];
    sfcnStart(rts);
    if (ssGetErrorStatus(rts) != (NULL))
      return;
  }

  /* Start for S-Function (sg_fpga_IO397_da): '<S5>/IO397 Analog Output' */
  /* Level2 S-Function Block: '<S5>/IO397 Analog Output' (sg_fpga_IO397_da) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[4];
    sfcnStart(rts);
    if (ssGetErrorStatus(rts) != (NULL))
      return;
  }

  {
    int32_T Ns;
    int32_T i;
    static const int8_T Ns_0[6] = { 0, -5, -10, -15, -20, -25 };

    rtw_slrealtime_mutex_init
      (&speedgoat_test_SN10564_R2024a_M->Timing.semIdForTask1);

    /* InitializeConditions for DiscretePulseGenerator: '<S3>/Pulse Gen DIO' */
    for (i = 0; i < 6; i++) {
      Ns = Ns_0[i];
      speedgoat_test_SN10564_R2024a_DW.clockTickCounter[i] = Ns;
    }

    /* End of InitializeConditions for DiscretePulseGenerator: '<S3>/Pulse Gen DIO' */

    /* SystemInitialize for S-Function (slhwinterrupt): '<S4>/Interrupt Setup 1' incorporates:
     *  SubSystem: '<S4>/Function-Call Subsystem'
     */
    /* System initialize for function-call system: '<S4>/Function-Call Subsystem' */
    rtw_slrealtime_mutex_lock
      (speedgoat_test_SN10564_R2024a_M->Timing.semIdForTask1);
    speedgoat_test_SN10564_R2024a_M->Timing.clockTick1 =
      speedgoat_test_SN10564_R2024a_M->Timing.rtmClockTickBuf1;
    speedgoat_test_SN10564_R2024a_M->Timing.clockTickH1 =
      speedgoat_test_SN10564_R2024a_M->Timing.rtmBufClockTickBufH1;
    rtw_slrealtime_mutex_unlock
      (speedgoat_test_SN10564_R2024a_M->Timing.semIdForTask1);

    /* Start for S-Function (sg_fpga_inta_sf_a1): '<S6>/CoS Interrupt' */
    /* Level2 S-Function Block: '<S6>/CoS Interrupt' (sg_fpga_inta_sf_a1) */
    {
      SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[0];
      sfcnStart(rts);
      if (ssGetErrorStatus(rts) != (NULL))
        return;
    }

    /* InitializeConditions for UnitDelay: '<S7>/Output' */
    speedgoat_test_SN10564_R2024a_DW.Output_DSTATE =
      speedgoat_test_SN10564_R202_cal->Output_InitialCondition;

    /* SystemInitialize for UnitDelay: '<S7>/Output' incorporates:
     *  Outport: '<S6>/Out1'
     */
    speedgoat_test_SN10564_R2024a_B.Output =
      speedgoat_test_SN10564_R202_cal->Out1_Y0;

    // Initialize the sigevent structs.  One for no wakeup and the other
    // when the board did interrupt.
    SIGEV_NONE_INIT( &S4_InterruptSetup1_D.sig_none );

    // S4_InterruptSetup1_D.sig_pulse is initialized each time the interrupt
    // occurs so we can send the incrementing count.

    // With a defined PCI map function, use the IRQ from QNX.
    // Need to test for error return here.  Since the hook function
    // can be in C, an error won't throw, but will return a negative number.
    // *_D.context gets a pointer to a context, which would be pci addresses
    // mapped to virtual memory for a hardware board.
    // For interrupt mode with hardware, IRQ is meaningful and .context
    // will contain mapped addresses to talk to the board.
    // For polling hardware, IRQ is not used and .context is still mapped
    // addresses to talk to the board.
    // For polling XCP or some other out-of-model condition, then IRQ
    // is also ignored and .context is a pointer to context for that other
    // condition we want to find.  If this 'software device' doesn't
    // need any context, then just specify mapper as "none".

    // We call the map function if it exists for all 4 permutations.
    // Int or polling, function or model.
    S4_InterruptSetup1_D.IRQ = IO397_50k_map_public
      ( &S4_InterruptSetup1_D.context, 16776961 );
    if (S4_InterruptSetup1_D.IRQ < 0 ) {
      sprintf( S4_InterruptSetup1_errmsg,
              "Fatal error when configuring the interrupt or polling source in $<Name>\n"
              );
      rtmSetErrorStatus(speedgoat_test_SN10564_R2024a_M,
                        S4_InterruptSetup1_errmsg);
    }

    // Priority is ignored in the sigevent because the connection is set up with priority
    // inheritance turned off.  But since we need to send it to codegen
    // adding it to the sigevent incurs no extra overhead.
    S4_InterruptSetup1_D.pri = 254;

    // TaskID is 1 for S4_InterruptSetup1_fc
    {
      // 1.  Attach the ISR to the IRQ we got from the map function
      uint32_T ret = InterruptAttach_r( S4_InterruptSetup1_D.IRQ,
        S4_InterruptSetup1_ISR,
        nullptr,
        0,
        0);
      if (ret >= 0 )                // ret is the interrupt ID, needed by detach
        S4_InterruptSetup1_D.intrID = ret;
      else                            // ret is the negative of the error number
      {
        sprintf( S4_InterruptSetup1_errmsg,
                "Error attaching interrupt for block <S4>/Interrupt Setup 1: %s\n",
                strerror( -1*ret ) );
        rtmSetErrorStatus(speedgoat_test_SN10564_R2024a_M,
                          S4_InterruptSetup1_errmsg);
      }

      slrealtime::SetInterruptMode( 1 );
      slrealtime::StartCallbackService::registerCB( std::bind
        ( S4_InterruptSetup1_callback ), -100 );
    }
  }

  /* Enable for Sin: '<S5>/Sine Wave' */
  speedgoat_test_SN10564_R2024a_DW.systemEnable = 1;
}

/* Model terminate function */
void speedgoat_test_SN10564_R2024a_terminate(void)
{
  /* user code (Terminate function Header) */
  {
    // stop the board from interrupting, changing status or doing DMA transfers.
    IO397_50k_stop_public( S4_InterruptSetup1_D.context );

    // Detach the interrupt
    uint32_T ret = InterruptDetach_r( S4_InterruptSetup1_D.intrID );
    if (ret != EOK ) {
      sprintf( S4_InterruptSetup1_errmsg,
              "Error detaching interrupt for block <S4>/Interrupt Setup 1: %s\n",
              strerror( ret ) );
      rtmSetErrorStatus(speedgoat_test_SN10564_R2024a_M,
                        S4_InterruptSetup1_errmsg);
    }
  }

  rtw_slrealtime_mutex_destroy
    (speedgoat_test_SN10564_R2024a_M->Timing.semIdForTask1);

  /* Terminate for S-Function (sg_fpga_di_sf_a2): '<S3>/Digital input' */
  /* Level2 S-Function Block: '<S3>/Digital input' (sg_fpga_di_sf_a2) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[1];
    sfcnTerminate(rts);
  }

  /* Terminate for S-Function (sg_fpga_do_sf_a2): '<S3>/Digital output' */
  /* Level2 S-Function Block: '<S3>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[2];
    sfcnTerminate(rts);
  }

  /* Terminate for S-Function (slhwinterrupt): '<S4>/Interrupt Setup 1' incorporates:
   *  SubSystem: '<S4>/Function-Call Subsystem'
   */

  /* Termination for function-call system: '<S4>/Function-Call Subsystem' */

  /* Terminate for S-Function (sg_fpga_inta_sf_a1): '<S6>/CoS Interrupt' */
  /* Level2 S-Function Block: '<S6>/CoS Interrupt' (sg_fpga_inta_sf_a1) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[0];
    sfcnTerminate(rts);
  }

  /* End of Terminate for S-Function (slhwinterrupt): '<S4>/Interrupt Setup 1' */

  /* Terminate for S-Function (sg_fpga_IO397_ad): '<S5>/IO397 Analog Input' */
  /* Level2 S-Function Block: '<S5>/IO397 Analog Input' (sg_fpga_IO397_ad) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[3];
    sfcnTerminate(rts);
  }

  /* Terminate for S-Function (sg_fpga_IO397_da): '<S5>/IO397 Analog Output' */
  /* Level2 S-Function Block: '<S5>/IO397 Analog Output' (sg_fpga_IO397_da) */
  {
    SimStruct *rts = speedgoat_test_SN10564_R2024a_M->childSfunctions[4];
    sfcnTerminate(rts);
  }

  /* user code (Terminate function Trailer) */
  {
    uintptr_t bar2Addr;
    volatile io3xx_pull *ptrIO31x_pull;
    volatile io3xx_2x *ptrio3xx_2x;
    uint16_t moduleArchitecture;
    sg_fpga_io3xxModuleIdT moduleId;
    static char msg[500];

    // Get module IDs (PIC info)
    sg_fpga_IO3xxGetModuleId(39750, &moduleId);
    moduleArchitecture = moduleId.moduleArchitecture;
    SG_PRINTF(DEBUG, "moduleArchitecture %d\n",moduleArchitecture);
    if (moduleArchitecture == TEWS_TXMC) {
      // Get pointer to io31x_pull
      bar2Addr = (uintptr_t)io3xxGetAddressSgLib((int32_t)1, SG_FPGA_IO3XX_BAR2);
      if (bar2Addr == 0) {
        sprintf(msg, "%s", pSgErrorStr);
        rtmSetErrorStatus(speedgoat_test_SN10564_R2024a_M, msg);
        SG_PRINTF(ERROR,msg);
        return;
      }

      ptrIO31x_pull = (io3xx_pull *)((uintptr_t)bar2Addr + IO3xx_PULL_BASE);

      // Disable pull resistors
      ptrIO31x_pull->enable = 0x0;     // disable
    }

    // Pull down and disable DIOs
    if ((1 == 2) || (1 == 3)) {
      bar2Addr = (uintptr_t)io3xxGetAddressSgLib((int32_t)1, SG_FPGA_IO3XX_BAR2);
      if (bar2Addr == 0) {
        sprintf(msg, "%s", pSgErrorStr);
        rtmSetErrorStatus(speedgoat_test_SN10564_R2024a_M, msg);
        SG_PRINTF(ERROR,msg);
        return;
      }

      ptrio3xx_2x = (io3xx_2x *)((uintptr_t)bar2Addr +IO3xx_2x_BASE);
      ptrio3xx_2x->pull = 0xffffffff;  // pull down
      ptrio3xx_2x->dir = 0x0;          // input
      ptrio3xx_2x->update = 0x1;
      sg_wait_s(SG_FPGA_WAIT_TIME_100us);
      ptrio3xx_2x->update = 0x0;
      sg_wait_s(SG_FPGA_WAIT_TIME_1ms);

#if DEBUGGING

      // For debugging output port register of IO-Expander
      sg_wait_s(SG_FPGA_WAIT_TIME_100ms);
      SG_PRINTF(INFO, "last configuration from mdl start\n");
      SG_PRINTF(INFO, "rxData of Expander1: 0x%X\n",
                ptrio3xx_2x->rxDataExpander1);
      SG_PRINTF(INFO, "rxData of Expander2: 0x%X\n",
                ptrio3xx_2x->rxDataExpander2);
      SG_PRINTF(INFO, "rxData of Expander3: 0x%X\n",
                ptrio3xx_2x->rxDataExpander3);
      SG_PRINTF(INFO, "rxData of Expander4: 0x%X\n",
                ptrio3xx_2x->rxDataExpander4);

#endif

    } else if (1 == 4) {
      IO3xx_24_terminate(1);
    }

    freeFPGAModuleSgLib((uint32_t)1);
  }
}
