/*
 * Test_LOGICA_3FPWM.cpp
 *
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * Code generation for model "Test_LOGICA_3FPWM".
 *
 * Model version              : 1.48
 * Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
 * C++ source code generated on : Wed Jul 23 11:33:04 2025
 *
 * Target selection: speedgoat.tlc
 * Note: GRT includes extra infrastructure and instrumentation for prototyping
 * Embedded hardware selection: Intel->x86-64 (Linux 64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#include "Test_LOGICA_3FPWM.h"
#include "Test_LOGICA_3FPWM_cal.h"
#include "Test_LOGICA_3FPWM_private.h"
#include "rtwtypes.h"
#include <cstring>

extern "C"
{

#include "rt_nonfinite.h"

}

#include <cmath>
#include <cfloat>

/* Block signals (default storage) */
B_Test_LOGICA_3FPWM_T Test_LOGICA_3FPWM_B;

/* Block states (default storage) */
DW_Test_LOGICA_3FPWM_T Test_LOGICA_3FPWM_DW;

/* Real-time model */
RT_MODEL_Test_LOGICA_3FPWM_T Test_LOGICA_3FPWM_M_ = RT_MODEL_Test_LOGICA_3FPWM_T
  ();
RT_MODEL_Test_LOGICA_3FPWM_T *const Test_LOGICA_3FPWM_M = &Test_LOGICA_3FPWM_M_;
real_T look1_pbinlxpw(real_T u0, const real_T bp0[], const real_T table[],
                      uint32_T prevIndex[], uint32_T maxIndex)
{
  real_T frac;
  real_T yL_0d0;
  uint32_T bpIdx;

  /* Column-major Lookup 1-D
     Search method: 'binary'
     Use previous index: 'on'
     Interpolation method: 'Linear point-slope'
     Extrapolation method: 'Linear'
     Use last breakpoint for index at or above upper limit: 'off'
     Remove protection against out-of-range input in generated code: 'off'
   */
  /* Prelookup - Index and Fraction
     Index Search method: 'binary'
     Extrapolation method: 'Linear'
     Use previous index: 'on'
     Use last breakpoint for index at or above upper limit: 'off'
     Remove protection against out-of-range input in generated code: 'off'
   */
  if (u0 <= bp0[0U]) {
    bpIdx = 0U;
    frac = (u0 - bp0[0U]) / (bp0[1U] - bp0[0U]);
  } else if (u0 < bp0[maxIndex]) {
    uint32_T found;
    uint32_T iLeft;
    uint32_T iRght;

    /* Binary Search using Previous Index */
    bpIdx = prevIndex[0U];
    iLeft = 0U;
    iRght = maxIndex;
    found = 0U;
    while (found == 0U) {
      if (u0 < bp0[bpIdx]) {
        iRght = bpIdx - 1U;
        bpIdx = ((bpIdx + iLeft) - 1U) >> 1U;
      } else if (u0 < bp0[bpIdx + 1U]) {
        found = 1U;
      } else {
        iLeft = bpIdx + 1U;
        bpIdx = ((bpIdx + iRght) + 1U) >> 1U;
      }
    }

    frac = (u0 - bp0[bpIdx]) / (bp0[bpIdx + 1U] - bp0[bpIdx]);
  } else {
    bpIdx = maxIndex - 1U;
    frac = (u0 - bp0[maxIndex - 1U]) / (bp0[maxIndex] - bp0[maxIndex - 1U]);
  }

  prevIndex[0U] = bpIdx;

  /* Column-major Interpolation 1-D
     Interpolation method: 'Linear point-slope'
     Use last breakpoint for index at or above upper limit: 'off'
     Overflow mode: 'portable wrapping'
   */
  yL_0d0 = table[bpIdx];
  return (table[bpIdx + 1U] - yL_0d0) * frac + yL_0d0;
}

real_T rt_remd_snf(real_T u0, real_T u1)
{
  real_T y;
  if (rtIsNaN(u0) || rtIsNaN(u1) || rtIsInf(u0)) {
    y = (rtNaN);
  } else if (rtIsInf(u1)) {
    y = u0;
  } else {
    if (u1 < 0.0) {
      y = std::ceil(u1);
    } else {
      y = std::floor(u1);
    }

    if ((u1 != 0.0) && (u1 != y)) {
      real_T q;
      q = std::abs(u0 / u1);
      if (!(std::abs(q - std::floor(q + 0.5)) > DBL_EPSILON * q)) {
        y = 0.0 * u0;
      } else {
        y = std::fmod(u0, u1);
      }
    } else {
      y = std::fmod(u0, u1);
    }
  }

  return y;
}

/* Model step function */
void Test_LOGICA_3FPWM_step(void)
{
  /* DigitalClock: '<S11>/Digital Clock' */
  Test_LOGICA_3FPWM_B.DigitalClock = Test_LOGICA_3FPWM_M->Timing.t[0];

  /* Sum: '<S11>/Add1' incorporates:
   *  Constant: '<S11>/Constant3'
   */
  Test_LOGICA_3FPWM_B.Add1 = Test_LOGICA_3FPWM_B.DigitalClock +
    Test_LOGICA_3FPWM_cal->Constant3_Value;

  /* Math: '<S11>/Math Function' incorporates:
   *  Constant: '<S11>/Constant1'
   */
  Test_LOGICA_3FPWM_B.MathFunction = rt_remd_snf(Test_LOGICA_3FPWM_B.Add1,
    Test_LOGICA_3FPWM_cal->Constant1_Value);

  /* Gain: '<S11>/1\ib1' */
  Test_LOGICA_3FPWM_B.uib1 = Test_LOGICA_3FPWM_cal->uib1_Gain *
    Test_LOGICA_3FPWM_B.MathFunction;

  /* Lookup_n-D: '<S11>/1-D Lookup Table' incorporates:
   *  Gain: '<S11>/1\ib1'
   */
  Test_LOGICA_3FPWM_B.uDLookupTable = look1_pbinlxpw(Test_LOGICA_3FPWM_B.uib1,
    Test_LOGICA_3FPWM_cal->uDLookupTable_bp01Data,
    Test_LOGICA_3FPWM_cal->uDLookupTable_tableData,
    &Test_LOGICA_3FPWM_DW.m_bpIndex, 2U);

  /* Sum: '<S11>/Add3' incorporates:
   *  Constant: '<S11>/Constant2'
   */
  Test_LOGICA_3FPWM_B.Add3 = Test_LOGICA_3FPWM_B.uDLookupTable -
    Test_LOGICA_3FPWM_cal->Constant2_Value;

  /* Sum: '<S2>/Add3' incorporates:
   *  Constant: '<S1>/Constant10'
   */
  Test_LOGICA_3FPWM_B.Add3_j = Test_LOGICA_3FPWM_cal->PWMGenerator2Level_MinMax
    [1] - Test_LOGICA_3FPWM_cal->PWMGenerator2Level_MinMax[0];

  /* Gain: '<S2>/Gain1' */
  Test_LOGICA_3FPWM_B.Gain1 = Test_LOGICA_3FPWM_cal->Gain1_Gain *
    Test_LOGICA_3FPWM_B.Add3_j;

  /* Product: '<S2>/MUL1' */
  Test_LOGICA_3FPWM_B.MUL1 = Test_LOGICA_3FPWM_B.Add3 *
    Test_LOGICA_3FPWM_B.Gain1;

  /* Sum: '<S2>/Add4' incorporates:
   *  Constant: '<S1>/Constant10'
   */
  Test_LOGICA_3FPWM_B.Add4 = (Test_LOGICA_3FPWM_cal->PWMGenerator2Level_MinMax[0]
    + Test_LOGICA_3FPWM_B.MUL1) + Test_LOGICA_3FPWM_B.Gain1;

  /* RelationalOperator: '<S6>/Relational Operator2' incorporates:
   *  Constant: '<Root>/Va'
   *  Constant: '<Root>/Vb'
   *  Constant: '<Root>/Vc'
   */
  Test_LOGICA_3FPWM_B.RelationalOperator2[0] = (Test_LOGICA_3FPWM_cal->Va_Value >=
    Test_LOGICA_3FPWM_B.Add4);
  Test_LOGICA_3FPWM_B.RelationalOperator2[1] = (Test_LOGICA_3FPWM_cal->Vb_Value >=
    Test_LOGICA_3FPWM_B.Add4);
  Test_LOGICA_3FPWM_B.RelationalOperator2[2] = (Test_LOGICA_3FPWM_cal->Vc_Value >=
    Test_LOGICA_3FPWM_B.Add4);

  /* Logic: '<S1>/Logical Operator4' */
  Test_LOGICA_3FPWM_B.LogicalOperator4[0] =
    !Test_LOGICA_3FPWM_B.RelationalOperator2[0];
  Test_LOGICA_3FPWM_B.LogicalOperator4[1] =
    !Test_LOGICA_3FPWM_B.RelationalOperator2[1];
  Test_LOGICA_3FPWM_B.LogicalOperator4[2] =
    !Test_LOGICA_3FPWM_B.RelationalOperator2[2];

  /* DataTypeConversion: '<S1>/Data Type Conversion' */
  Test_LOGICA_3FPWM_B.DataTypeConversion[0] =
    Test_LOGICA_3FPWM_B.RelationalOperator2[0];
  Test_LOGICA_3FPWM_B.DataTypeConversion[1] =
    Test_LOGICA_3FPWM_B.LogicalOperator4[0];
  Test_LOGICA_3FPWM_B.DataTypeConversion[2] =
    Test_LOGICA_3FPWM_B.RelationalOperator2[1];
  Test_LOGICA_3FPWM_B.DataTypeConversion[3] =
    Test_LOGICA_3FPWM_B.LogicalOperator4[1];
  Test_LOGICA_3FPWM_B.DataTypeConversion[4] =
    Test_LOGICA_3FPWM_B.RelationalOperator2[2];
  Test_LOGICA_3FPWM_B.DataTypeConversion[5] =
    Test_LOGICA_3FPWM_B.LogicalOperator4[2];

  /* S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */

  /* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = Test_LOGICA_3FPWM_M->childSfunctions[0];
    sfcnOutputs(rts,0);
  }

  /* user code (Output function Trailer) */
  {
  }

  /* Update absolute time for base rate */
  /* The "clockTick0" counts the number of times the code of this task has
   * been executed. The absolute time is the multiplication of "clockTick0"
   * and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
   * overflow during the application lifespan selected.
   * Timer of this task consists of two 32 bit unsigned integers.
   * The two integers represent the low bits Timing.clockTick0 and the high bits
   * Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
   */
  if (!(++Test_LOGICA_3FPWM_M->Timing.clockTick0)) {
    ++Test_LOGICA_3FPWM_M->Timing.clockTickH0;
  }

  Test_LOGICA_3FPWM_M->Timing.t[0] = Test_LOGICA_3FPWM_M->Timing.clockTick0 *
    Test_LOGICA_3FPWM_M->Timing.stepSize0 +
    Test_LOGICA_3FPWM_M->Timing.clockTickH0 *
    Test_LOGICA_3FPWM_M->Timing.stepSize0 * 4294967296.0;
}

/* Model initialize function */
void Test_LOGICA_3FPWM_initialize(void)
{
  /* Registration code */

  /* initialize non-finites */
  rt_InitInfAndNaN(sizeof(real_T));
  rtsiSetSolverName(&Test_LOGICA_3FPWM_M->solverInfo,"FixedStepDiscrete");
  Test_LOGICA_3FPWM_M->solverInfoPtr = (&Test_LOGICA_3FPWM_M->solverInfo);

  /* Initialize timing info */
  {
    int_T *mdlTsMap = Test_LOGICA_3FPWM_M->Timing.sampleTimeTaskIDArray;
    mdlTsMap[0] = 0;
    Test_LOGICA_3FPWM_M->Timing.sampleTimeTaskIDPtr = (&mdlTsMap[0]);
    Test_LOGICA_3FPWM_M->Timing.sampleTimes =
      (&Test_LOGICA_3FPWM_M->Timing.sampleTimesArray[0]);
    Test_LOGICA_3FPWM_M->Timing.offsetTimes =
      (&Test_LOGICA_3FPWM_M->Timing.offsetTimesArray[0]);

    /* task periods */
    Test_LOGICA_3FPWM_M->Timing.sampleTimes[0] = (5.0E-5);

    /* task offsets */
    Test_LOGICA_3FPWM_M->Timing.offsetTimes[0] = (0.0);
  }

  rtmSetTPtr(Test_LOGICA_3FPWM_M, &Test_LOGICA_3FPWM_M->Timing.tArray[0]);

  {
    int_T *mdlSampleHits = Test_LOGICA_3FPWM_M->Timing.sampleHitArray;
    mdlSampleHits[0] = 1;
    Test_LOGICA_3FPWM_M->Timing.sampleHits = (&mdlSampleHits[0]);
  }

  rtmSetTFinal(Test_LOGICA_3FPWM_M, -1);
  Test_LOGICA_3FPWM_M->Timing.stepSize0 = 5.0E-5;
  Test_LOGICA_3FPWM_M->solverInfoPtr = (&Test_LOGICA_3FPWM_M->solverInfo);
  Test_LOGICA_3FPWM_M->Timing.stepSize = (5.0E-5);
  rtsiSetFixedStepSize(&Test_LOGICA_3FPWM_M->solverInfo, 5.0E-5);
  rtsiSetSolverMode(&Test_LOGICA_3FPWM_M->solverInfo, SOLVER_MODE_SINGLETASKING);

  /* block I/O */
  (void) std::memset((static_cast<void *>(&Test_LOGICA_3FPWM_B)), 0,
                     sizeof(B_Test_LOGICA_3FPWM_T));

  /* states (dwork) */
  (void) std::memset(static_cast<void *>(&Test_LOGICA_3FPWM_DW), 0,
                     sizeof(DW_Test_LOGICA_3FPWM_T));

  /* child S-Function registration */
  {
    RTWSfcnInfo *sfcnInfo = &Test_LOGICA_3FPWM_M->NonInlinedSFcns.sfcnInfo;
    Test_LOGICA_3FPWM_M->sfcnInfo = (sfcnInfo);
    rtssSetErrorStatusPtr(sfcnInfo, (&rtmGetErrorStatus(Test_LOGICA_3FPWM_M)));
    Test_LOGICA_3FPWM_M->Sizes.numSampTimes = (1);
    rtssSetNumRootSampTimesPtr(sfcnInfo,
      &Test_LOGICA_3FPWM_M->Sizes.numSampTimes);
    Test_LOGICA_3FPWM_M->NonInlinedSFcns.taskTimePtrs[0] = (&rtmGetTPtr
      (Test_LOGICA_3FPWM_M)[0]);
    rtssSetTPtrPtr(sfcnInfo,Test_LOGICA_3FPWM_M->NonInlinedSFcns.taskTimePtrs);
    rtssSetTStartPtr(sfcnInfo, &rtmGetTStart(Test_LOGICA_3FPWM_M));
    rtssSetTFinalPtr(sfcnInfo, &rtmGetTFinal(Test_LOGICA_3FPWM_M));
    rtssSetTimeOfLastOutputPtr(sfcnInfo, &rtmGetTimeOfLastOutput
      (Test_LOGICA_3FPWM_M));
    rtssSetStepSizePtr(sfcnInfo, &Test_LOGICA_3FPWM_M->Timing.stepSize);
    rtssSetStopRequestedPtr(sfcnInfo, &rtmGetStopRequested(Test_LOGICA_3FPWM_M));
    rtssSetDerivCacheNeedsResetPtr(sfcnInfo,
      &Test_LOGICA_3FPWM_M->derivCacheNeedsReset);
    rtssSetZCCacheNeedsResetPtr(sfcnInfo,
      &Test_LOGICA_3FPWM_M->zCCacheNeedsReset);
    rtssSetContTimeOutputInconsistentWithStateAtMajorStepPtr(sfcnInfo,
      &Test_LOGICA_3FPWM_M->CTOutputIncnstWithState);
    rtssSetSampleHitsPtr(sfcnInfo, &Test_LOGICA_3FPWM_M->Timing.sampleHits);
    rtssSetPerTaskSampleHitsPtr(sfcnInfo,
      &Test_LOGICA_3FPWM_M->Timing.perTaskSampleHits);
    rtssSetSimModePtr(sfcnInfo, &Test_LOGICA_3FPWM_M->simMode);
    rtssSetSolverInfoPtr(sfcnInfo, &Test_LOGICA_3FPWM_M->solverInfoPtr);
  }

  Test_LOGICA_3FPWM_M->Sizes.numSFcns = (1);

  /* register each child */
  {
    (void) std::memset(static_cast<void *>
                       (&Test_LOGICA_3FPWM_M->NonInlinedSFcns.childSFunctions[0]),
                       0,
                       1*sizeof(SimStruct));
    Test_LOGICA_3FPWM_M->childSfunctions =
      (&Test_LOGICA_3FPWM_M->NonInlinedSFcns.childSFunctionPtrs[0]);
    Test_LOGICA_3FPWM_M->childSfunctions[0] =
      (&Test_LOGICA_3FPWM_M->NonInlinedSFcns.childSFunctions[0]);

    /* Level2 S-Function Block: Test_LOGICA_3FPWM/<Root>/Digital output (sg_fpga_do_sf_a2) */
    {
      SimStruct *rts = Test_LOGICA_3FPWM_M->childSfunctions[0];

      /* timing info */
      time_T *sfcnPeriod = Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.sfcnPeriod;
      time_T *sfcnOffset = Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.sfcnOffset;
      int_T *sfcnTsMap = Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.blkInfo2[0]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &Test_LOGICA_3FPWM_M->NonInlinedSFcns.inputOutputPortInfo2[0]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, Test_LOGICA_3FPWM_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.methods2[0]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.methods3[0]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.methods4[0]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.statesInfo2
                         [0]);
        ssSetPeriodicStatesInfo(rts,
          &Test_LOGICA_3FPWM_M->NonInlinedSFcns.periodicStatesInfo[0]);
      }

      /* inputs */
      {
        _ssSetNumInputPorts(rts, 6);
        ssSetPortInfoForInputs(rts,
          &Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
        ssSetPortInfoForInputs(rts,
          &Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
        _ssSetPortInfo2ForInputUnits(rts,
          &Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.inputPortUnits[0]);
        ssSetInputPortUnit(rts, 0, 0);
        ssSetInputPortUnit(rts, 1, 0);
        ssSetInputPortUnit(rts, 2, 0);
        ssSetInputPortUnit(rts, 3, 0);
        ssSetInputPortUnit(rts, 4, 0);
        ssSetInputPortUnit(rts, 5, 0);
        _ssSetPortInfo2ForInputCoSimAttribute(rts,
          &Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.inputPortCoSimAttribute[0]);
        ssSetInputPortIsContinuousQuantity(rts, 0, 0);
        ssSetInputPortIsContinuousQuantity(rts, 1, 0);
        ssSetInputPortIsContinuousQuantity(rts, 2, 0);
        ssSetInputPortIsContinuousQuantity(rts, 3, 0);
        ssSetInputPortIsContinuousQuantity(rts, 4, 0);
        ssSetInputPortIsContinuousQuantity(rts, 5, 0);

        /* port 0 */
        {
          ssSetInputPortRequiredContiguous(rts, 0, 1);
          ssSetInputPortSignal(rts, 0, &Test_LOGICA_3FPWM_B.DataTypeConversion[0]);
          _ssSetInputPortNumDimensions(rts, 0, 1);
          ssSetInputPortWidthAsInt(rts, 0, 1);
        }

        /* port 1 */
        {
          ssSetInputPortRequiredContiguous(rts, 1, 1);
          ssSetInputPortSignal(rts, 1, &Test_LOGICA_3FPWM_B.DataTypeConversion[1]);
          _ssSetInputPortNumDimensions(rts, 1, 1);
          ssSetInputPortWidthAsInt(rts, 1, 1);
        }

        /* port 2 */
        {
          ssSetInputPortRequiredContiguous(rts, 2, 1);
          ssSetInputPortSignal(rts, 2, &Test_LOGICA_3FPWM_B.DataTypeConversion[2]);
          _ssSetInputPortNumDimensions(rts, 2, 1);
          ssSetInputPortWidthAsInt(rts, 2, 1);
        }

        /* port 3 */
        {
          ssSetInputPortRequiredContiguous(rts, 3, 1);
          ssSetInputPortSignal(rts, 3, &Test_LOGICA_3FPWM_B.DataTypeConversion[3]);
          _ssSetInputPortNumDimensions(rts, 3, 1);
          ssSetInputPortWidthAsInt(rts, 3, 1);
        }

        /* port 4 */
        {
          ssSetInputPortRequiredContiguous(rts, 4, 1);
          ssSetInputPortSignal(rts, 4, &Test_LOGICA_3FPWM_B.DataTypeConversion[4]);
          _ssSetInputPortNumDimensions(rts, 4, 1);
          ssSetInputPortWidthAsInt(rts, 4, 1);
        }

        /* port 5 */
        {
          ssSetInputPortRequiredContiguous(rts, 5, 1);
          ssSetInputPortSignal(rts, 5, &Test_LOGICA_3FPWM_B.DataTypeConversion[5]);
          _ssSetInputPortNumDimensions(rts, 5, 1);
          ssSetInputPortWidthAsInt(rts, 5, 1);
        }
      }

      /* path info */
      ssSetModelName(rts, "Digital output");
      ssSetPath(rts, "Test_LOGICA_3FPWM/Digital output");
      ssSetRTModel(rts,Test_LOGICA_3FPWM_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.params;
        ssSetSFcnParamsCount(rts, 6);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)
                       Test_LOGICA_3FPWM_cal->Digitaloutput_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)
                       Test_LOGICA_3FPWM_cal->Digitaloutput_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)
                       Test_LOGICA_3FPWM_cal->Digitaloutput_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)
                       Test_LOGICA_3FPWM_cal->Digitaloutput_P4_Size);
        ssSetSFcnParam(rts, 4, (mxArray*)
                       Test_LOGICA_3FPWM_cal->Digitaloutput_P5_Size);
        ssSetSFcnParam(rts, 5, (mxArray*)
                       Test_LOGICA_3FPWM_cal->Digitaloutput_P6_Size);
      }

      /* work vectors */
      ssSetIWork(rts, (int_T *) &Test_LOGICA_3FPWM_DW.Digitaloutput_IWORK);
      ssSetPWork(rts, (void **) &Test_LOGICA_3FPWM_DW.Digitaloutput_PWORK[0]);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 2);

        /* IWORK */
        ssSetDWorkWidthAsInt(rts, 0, 1);
        ssSetDWorkDataType(rts, 0,SS_INTEGER);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0, &Test_LOGICA_3FPWM_DW.Digitaloutput_IWORK);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 1, 2);
        ssSetDWorkDataType(rts, 1,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 1, 0);
        ssSetDWork(rts, 1, &Test_LOGICA_3FPWM_DW.Digitaloutput_PWORK[0]);
      }

      /* registration */
      sg_fpga_do_sf_a2(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, 5.0E-5);
      ssSetOffsetTime(rts, 0, 0.0);
      sfcnTsMap[0] = 0;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      _ssSetInputPortConnected(rts, 0, 1);
      _ssSetInputPortConnected(rts, 1, 1);
      _ssSetInputPortConnected(rts, 2, 1);
      _ssSetInputPortConnected(rts, 3, 1);
      _ssSetInputPortConnected(rts, 4, 1);
      _ssSetInputPortConnected(rts, 5, 1);

      /* Update the BufferDstPort flags for each input port */
      ssSetInputPortBufferDstPort(rts, 0, -1);
      ssSetInputPortBufferDstPort(rts, 1, -1);
      ssSetInputPortBufferDstPort(rts, 2, -1);
      ssSetInputPortBufferDstPort(rts, 3, -1);
      ssSetInputPortBufferDstPort(rts, 4, -1);
      ssSetInputPortBufferDstPort(rts, 5, -1);
    }
  }

  /* Start for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
  /* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = Test_LOGICA_3FPWM_M->childSfunctions[0];
    sfcnStart(rts);
    if (ssGetErrorStatus(rts) != (NULL))
      return;
  }
}

/* Model terminate function */
void Test_LOGICA_3FPWM_terminate(void)
{
  /* Terminate for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
  /* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = Test_LOGICA_3FPWM_M->childSfunctions[0];
    sfcnTerminate(rts);
  }

  /* user code (Terminate function Trailer) */
  {
    freeFPGAModuleSgLib((uint32_t)1);
  }
}
