/*
 * speedgoat_test_SN10564_R2024a.h
 *
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * Code generation for model "speedgoat_test_SN10564_R2024a".
 *
 * Model version              : 1.3
 * Simulink Coder version : 24.1 (R2024a) 19-Nov-2023
 * C++ source code generated on : Thu Nov  7 11:28:20 2024
 *
 * Target selection: speedgoat.tlc
 * Note: GRT includes extra infrastructure and instrumentation for prototyping
 * Embedded hardware selection: Intel->x86-64 (Linux 64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#ifndef speedgoat_test_SN10564_R2024a_h_
#define speedgoat_test_SN10564_R2024a_h_
#include <logsrv.h>
#include "rtwtypes.h"
#include "simstruc.h"
#include "fixedpoint.h"
#include "sys/siginfo.h"
#include "sys/neutrino.h"
#include "Logger.hpp"
#include "StartCallbackAPI.h"
#include "ModelInfo.hpp"
#include "sg_fpga_io30x_setup_util.h"
#include "sg_fpga_io31x_io32x_setup_util.h"
#include "sg_fpga_io33x_setup_util.h"
#include "sg_fpga_io36x_setup_util.h"
#include "sg_fpga_io39x_setup_util.h"
#include "sg_fpga_io3xx_scatter_gather_dma.h"
#include "sg_common.h"
#include "sg_printf.h"
#include "speedgoat_test_SN10564_R2024a_types.h"
#include <stddef.h>
#include "crl_mutex.hpp"
#include <cstring>
#include "speedgoat_test_SN10564_R2024a_cal.h"

extern "C"
{

#include "rt_nonfinite.h"

}

/* Macros for accessing real-time model data structure */
#ifndef rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag
#define rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm) ((rtm)->CTOutputIncnstWithState)
#endif

#ifndef rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag
#define rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm, val) ((rtm)->CTOutputIncnstWithState = (val))
#endif

#ifndef rtmGetDerivCacheNeedsReset
#define rtmGetDerivCacheNeedsReset(rtm) ((rtm)->derivCacheNeedsReset)
#endif

#ifndef rtmSetDerivCacheNeedsReset
#define rtmSetDerivCacheNeedsReset(rtm, val) ((rtm)->derivCacheNeedsReset = (val))
#endif

#ifndef rtmGetFinalTime
#define rtmGetFinalTime(rtm)           ((rtm)->Timing.tFinal)
#endif

#ifndef rtmGetSampleHitArray
#define rtmGetSampleHitArray(rtm)      ((rtm)->Timing.sampleHitArray)
#endif

#ifndef rtmGetStepSize
#define rtmGetStepSize(rtm)            ((rtm)->Timing.stepSize)
#endif

#ifndef rtmGetZCCacheNeedsReset
#define rtmGetZCCacheNeedsReset(rtm)   ((rtm)->zCCacheNeedsReset)
#endif

#ifndef rtmSetZCCacheNeedsReset
#define rtmSetZCCacheNeedsReset(rtm, val) ((rtm)->zCCacheNeedsReset = (val))
#endif

#ifndef rtmGet_TimeOfLastOutput
#define rtmGet_TimeOfLastOutput(rtm)   ((rtm)->Timing.timeOfLastOutput)
#endif

#ifndef rtmGetErrorStatus
#define rtmGetErrorStatus(rtm)         ((rtm)->errorStatus)
#endif

#ifndef rtmSetErrorStatus
#define rtmSetErrorStatus(rtm, val)    ((rtm)->errorStatus = (val))
#endif

#ifndef rtmGetStopRequested
#define rtmGetStopRequested(rtm)       ((rtm)->Timing.stopRequestedFlag)
#endif

#ifndef rtmSetStopRequested
#define rtmSetStopRequested(rtm, val)  ((rtm)->Timing.stopRequestedFlag = (val))
#endif

#ifndef rtmGetStopRequestedPtr
#define rtmGetStopRequestedPtr(rtm)    (&((rtm)->Timing.stopRequestedFlag))
#endif

#ifndef rtmGetT
#define rtmGetT(rtm)                   (rtmGetTPtr((rtm))[0])
#endif

#ifndef rtmGetTFinal
#define rtmGetTFinal(rtm)              ((rtm)->Timing.tFinal)
#endif

#ifndef rtmGetTPtr
#define rtmGetTPtr(rtm)                ((rtm)->Timing.t)
#endif

#ifndef rtmGetTStart
#define rtmGetTStart(rtm)              ((rtm)->Timing.tStart)
#endif

#ifndef rtmGetTimeOfLastOutput
#define rtmGetTimeOfLastOutput(rtm)    ((rtm)->Timing.timeOfLastOutput)
#endif

/* Block signals (default storage) */
struct B_speedgoat_test_SN10564_R2024a_T {
  real_T Digitalinput[5];              /* '<S3>/Digital input' */
  real_T IO397DI[5];                   /* '<S3>/Offset' */
  real_T PulseGenDIO[6];               /* '<S3>/Pulse Gen DIO' */
  real_T IO397AnalogInput_o1;          /* '<S5>/IO397 Analog Input' */
  real_T IO397AnalogInput_o2;          /* '<S5>/IO397 Analog Input' */
  real_T IO397AnalogInput_o3;          /* '<S5>/IO397 Analog Input' */
  real_T IO397AnalogInput_o4;          /* '<S5>/IO397 Analog Input' */
  real_T IO397_AI_CH01;                /* '<S5>/Gain1' */
  real_T IO397_AI_CH02;                /* '<S5>/Gain2' */
  real_T IO397_AI_CH03;                /* '<S5>/Gain3' */
  real_T IO397_AI_CH04;                /* '<S5>/Gain4' */
  real_T SineWave;                     /* '<S5>/Sine Wave' */
  uint32_T IO3xx_Interrupt;            /* '<S4>/Rate Transition' */
  uint32_T Output;                     /* '<S7>/Output' */
  uint32_T FixPtSum1;                  /* '<S8>/FixPt Sum1' */
  uint32_T FixPtSwitch;                /* '<S9>/FixPt Switch' */
};

/* Block states (default storage) for system '<Root>' */
struct DW_speedgoat_test_SN10564_R2024a_T {
  real_T lastSin;                      /* '<S5>/Sine Wave' */
  real_T lastCos;                      /* '<S5>/Sine Wave' */
  real_T CoSInterrupt_RWORK[16];       /* '<S6>/CoS Interrupt' */
  void *Digitalinput_PWORK[2];         /* '<S3>/Digital input' */
  struct {
    void *LoggedData;
  } Scope1_PWORK;                      /* '<S3>/Scope 1' */

  struct {
    void *AQHandles;
  } TAQSigLogging_InsertedFor_Offse;   /* synthesized block */

  void *Digitaloutput_PWORK[2];        /* '<S3>/Digital output' */
  struct {
    void *LoggedData;
  } Scope2_PWORK;                      /* '<S4>/Scope 2' */

  struct {
    void *AQHandles;
  } TAQSigLogging_InsertedFor_RateT;   /* synthesized block */

  void *IO397AnalogInput_PWORK[3];     /* '<S5>/IO397 Analog Input' */
  struct {
    void *LoggedData[4];
  } Scope3_PWORK;                      /* '<S5>/Scope 3' */

  struct {
    void *AQHandles;
  } TAQSigLogging_InsertedFor_Gain1;   /* synthesized block */

  struct {
    void *AQHandles;
  } TAQSigLogging_InsertedFor_Gain2;   /* synthesized block */

  struct {
    void *AQHandles;
  } TAQSigLogging_InsertedFor_Gain3;   /* synthesized block */

  struct {
    void *AQHandles;
  } TAQSigLogging_InsertedFor_Gain4;   /* synthesized block */

  void *IO397AnalogOutput_PWORK[2];    /* '<S5>/IO397 Analog Output' */
  struct {
    void *USERIO_P_IND;
    void *PROG_SPACE_P_IND;
    void *CONFIG_REGISTER_P_IND;
    void *CONDITIONING_MODULE_IO3xx_2x_P_IND;
    void *DEVICENAME_P_IND;
    void *DMA_CONTROLLER_P_IND;
  } Setup_PWORK;                       /* '<S1>/Setup' */

  void *CoSInterrupt_PWORK;            /* '<S6>/CoS Interrupt' */
  uint32_T Output_DSTATE;              /* '<S7>/Output' */
  int32_T clockTickCounter[6];         /* '<S3>/Pulse Gen DIO' */
  int32_T systemEnable;                /* '<S5>/Sine Wave' */
  int_T IO397AnalogOutput_IWORK;       /* '<S5>/IO397 Analog Output' */
  struct {
    int_T MODULEARCHITECTURE_I_IND;
  } Setup_IWORK;                       /* '<S1>/Setup' */

  int_T CoSInterrupt_IWORK;            /* '<S6>/CoS Interrupt' */
  int8_T FunctionCallSubsystem_SubsysRan;/* '<S4>/Function-Call Subsystem' */
};

/* Real-time Model Data Structure */
struct tag_RTM_speedgoat_test_SN10564_R2024a_T {
  struct SimStruct_tag * *childSfunctions;
  const char_T *errorStatus;
  SS_SimMode simMode;
  RTWSolverInfo solverInfo;
  RTWSolverInfo *solverInfoPtr;
  void *sfcnInfo;

  /*
   * NonInlinedSFcns:
   * The following substructure contains information regarding
   * non-inlined s-functions used in the model.
   */
  struct {
    RTWSfcnInfo sfcnInfo;
    time_T *taskTimePtrs[2];
    SimStruct childSFunctions[5];
    SimStruct *childSFunctionPtrs[5];
    struct _ssBlkInfo2 blkInfo2[5];
    struct _ssSFcnModelMethods2 methods2[5];
    struct _ssSFcnModelMethods3 methods3[5];
    struct _ssSFcnModelMethods4 methods4[5];
    struct _ssStatesInfo2 statesInfo2[5];
    ssPeriodicStatesInfo periodicStatesInfo[5];
    struct _ssPortInfo2 inputOutputPortInfo2[5];
    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      uint_T attribs[5];
      mxArray *params[5];
      struct _ssDWorkRecord dWork[3];
      struct _ssDWorkAuxRecord dWorkAux[3];
    } Sfcn0;

    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortOutputs outputPortInfo[1];
      struct _ssOutPortUnit outputPortUnits[1];
      struct _ssOutPortCoSimAttribute outputPortCoSimAttribute[1];
      uint_T attribs[4];
      mxArray *params[4];
      struct _ssDWorkRecord dWork[1];
      struct _ssDWorkAuxRecord dWorkAux[1];
    } Sfcn1;

    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortInputs inputPortInfo[1];
      struct _ssInPortUnit inputPortUnits[1];
      struct _ssInPortCoSimAttribute inputPortCoSimAttribute[1];
      uint_T attribs[6];
      mxArray *params[6];
      struct _ssDWorkRecord dWork[1];
      struct _ssDWorkAuxRecord dWorkAux[1];
    } Sfcn2;

    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortOutputs outputPortInfo[4];
      struct _ssOutPortUnit outputPortUnits[4];
      struct _ssOutPortCoSimAttribute outputPortCoSimAttribute[4];
      uint_T attribs[9];
      mxArray *params[9];
      struct _ssDWorkRecord dWork[1];
      struct _ssDWorkAuxRecord dWorkAux[1];
    } Sfcn3;

    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortInputs inputPortInfo[4];
      struct _ssInPortUnit inputPortUnits[4];
      struct _ssInPortCoSimAttribute inputPortCoSimAttribute[4];
      uint_T attribs[6];
      mxArray *params[6];
      struct _ssDWorkRecord dWork[2];
      struct _ssDWorkAuxRecord dWorkAux[2];
    } Sfcn4;
  } NonInlinedSFcns;

  boolean_T zCCacheNeedsReset;
  boolean_T derivCacheNeedsReset;
  boolean_T CTOutputIncnstWithState;

  /*
   * Sizes:
   * The following substructure contains sizes information
   * for many of the model attributes such as inputs, outputs,
   * dwork, sample times, etc.
   */
  struct {
    uint32_T options;
    int_T numContStates;
    int_T numU;
    int_T numY;
    int_T numSampTimes;
    int_T numBlocks;
    int_T numBlockIO;
    int_T numBlockPrms;
    int_T numDwork;
    int_T numSFcnPrms;
    int_T numSFcns;
    int_T numIports;
    int_T numOports;
    int_T numNonSampZCs;
    int_T sysDirFeedThru;
    int_T rtwGenSfcn;
  } Sizes;

  /*
   * Timing:
   * The following substructure contains information regarding
   * the timing information for the model.
   */
  struct {
    time_T stepSize;
    uint32_T clockTick0;
    uint32_T clockTickH0;
    time_T stepSize0;
    uint32_T clockTick1;
    uint32_T clockTickH1;
    time_T stepSize1;
    void *semIdForTask1;
    uint32_T rtmClockTickBuf1;
    uint32_T rtmBufClockTickBufH1;
    time_T tStart;
    time_T tFinal;
    time_T timeOfLastOutput;
    boolean_T stopRequestedFlag;
    time_T *sampleTimes;
    time_T *offsetTimes;
    int_T *sampleTimeTaskIDPtr;
    int_T *sampleHits;
    int_T *perTaskSampleHits;
    time_T *t;
    time_T sampleTimesArray[1];
    time_T offsetTimesArray[1];
    int_T sampleTimeTaskIDArray[1];
    int_T sampleHitArray[1];
    int_T perTaskSampleHitsArray[1];
    time_T tArray[2];
  } Timing;
};

/* Block signals (default storage) */
#ifdef __cplusplus

extern "C"
{

#endif

  extern struct B_speedgoat_test_SN10564_R2024a_T
    speedgoat_test_SN10564_R2024a_B;

#ifdef __cplusplus

}

#endif

/* Block states (default storage) */
extern struct DW_speedgoat_test_SN10564_R2024a_T
  speedgoat_test_SN10564_R2024a_DW;

#ifdef __cplusplus

extern "C"
{

#endif

  /* Model entry point functions */
  extern void speedgoat_test_SN10564_R2024a_initialize(void);
  extern void speedgoat_test_SN10564_R2024a_step(void);
  extern void speedgoat_test_SN10564_R2024a_terminate(void);

#ifdef __cplusplus

}

#endif

/* Real-time Model object */
#ifdef __cplusplus

extern "C"
{

#endif

  extern RT_MODEL_speedgoat_test_SN10564_R2024a_T *const
    speedgoat_test_SN10564_R2024a_M;

#ifdef __cplusplus

}

#endif

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'speedgoat_test_SN10564_R2024a'
 * '<S1>'   : 'speedgoat_test_SN10564_R2024a/IO397-50k'
 * '<S2>'   : 'speedgoat_test_SN10564_R2024a/info'
 * '<S3>'   : 'speedgoat_test_SN10564_R2024a/IO397-50k/DIO'
 * '<S4>'   : 'speedgoat_test_SN10564_R2024a/IO397-50k/INTA'
 * '<S5>'   : 'speedgoat_test_SN10564_R2024a/IO397-50k/IO39x_AD_DA'
 * '<S6>'   : 'speedgoat_test_SN10564_R2024a/IO397-50k/INTA/Function-Call Subsystem'
 * '<S7>'   : 'speedgoat_test_SN10564_R2024a/IO397-50k/INTA/Function-Call Subsystem/Counter Free-Running'
 * '<S8>'   : 'speedgoat_test_SN10564_R2024a/IO397-50k/INTA/Function-Call Subsystem/Counter Free-Running/Increment Real World'
 * '<S9>'   : 'speedgoat_test_SN10564_R2024a/IO397-50k/INTA/Function-Call Subsystem/Counter Free-Running/Wrap To Zero'
 */
#endif                                 /* speedgoat_test_SN10564_R2024a_h_ */
