/*
 * control_vectorial.h
 *
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * Code generation for model "control_vectorial".
 *
 * Model version              : 1.33
 * Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
 * C++ source code generated on : Mon Jul 28 10:28:03 2025
 *
 * Target selection: speedgoat.tlc
 * Note: GRT includes extra infrastructure and instrumentation for prototyping
 * Embedded hardware selection: Intel->x86-64 (Linux 64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#ifndef control_vectorial_h_
#define control_vectorial_h_
#include "rtwtypes.h"
#include "simstruc.h"
#include "fixedpoint.h"
#include "sg_fpga_io30x_setup_util.h"
#include "sg_fpga_io31x_io32x_setup_util.h"
#include "sg_fpga_io33x_setup_util.h"
#include "sg_fpga_io36x_setup_util.h"
#include "sg_fpga_io39x_setup_util.h"
#include "sg_fpga_io3xx_scatter_gather_dma.h"
#include "sg_fpga_nigora_setup_util.h"
#include "sg_common.h"
#include "sg_printf.h"
#include "control_vectorial_types.h"
#include <stddef.h>

extern "C"
{

#include "rtGetNaN.h"

}

#include <cstring>
#include "control_vectorial_cal.h"

extern "C"
{

#include "rt_nonfinite.h"

}

#include "zero_crossing_types.h"

/* Macros for accessing real-time model data structure */
#ifndef rtmGetContStateDisabled
#define rtmGetContStateDisabled(rtm)   ((rtm)->contStateDisabled)
#endif

#ifndef rtmSetContStateDisabled
#define rtmSetContStateDisabled(rtm, val) ((rtm)->contStateDisabled = (val))
#endif

#ifndef rtmGetContStates
#define rtmGetContStates(rtm)          ((rtm)->contStates)
#endif

#ifndef rtmSetContStates
#define rtmSetContStates(rtm, val)     ((rtm)->contStates = (val))
#endif

#ifndef rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag
#define rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm) ((rtm)->CTOutputIncnstWithState)
#endif

#ifndef rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag
#define rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm, val) ((rtm)->CTOutputIncnstWithState = (val))
#endif

#ifndef rtmGetDerivCacheNeedsReset
#define rtmGetDerivCacheNeedsReset(rtm) ((rtm)->derivCacheNeedsReset)
#endif

#ifndef rtmSetDerivCacheNeedsReset
#define rtmSetDerivCacheNeedsReset(rtm, val) ((rtm)->derivCacheNeedsReset = (val))
#endif

#ifndef rtmGetFinalTime
#define rtmGetFinalTime(rtm)           ((rtm)->Timing.tFinal)
#endif

#ifndef rtmGetIntgData
#define rtmGetIntgData(rtm)            ((rtm)->intgData)
#endif

#ifndef rtmSetIntgData
#define rtmSetIntgData(rtm, val)       ((rtm)->intgData = (val))
#endif

#ifndef rtmGetOdeF
#define rtmGetOdeF(rtm)                ((rtm)->odeF)
#endif

#ifndef rtmSetOdeF
#define rtmSetOdeF(rtm, val)           ((rtm)->odeF = (val))
#endif

#ifndef rtmGetOdeY
#define rtmGetOdeY(rtm)                ((rtm)->odeY)
#endif

#ifndef rtmSetOdeY
#define rtmSetOdeY(rtm, val)           ((rtm)->odeY = (val))
#endif

#ifndef rtmGetPeriodicContStateIndices
#define rtmGetPeriodicContStateIndices(rtm) ((rtm)->periodicContStateIndices)
#endif

#ifndef rtmSetPeriodicContStateIndices
#define rtmSetPeriodicContStateIndices(rtm, val) ((rtm)->periodicContStateIndices = (val))
#endif

#ifndef rtmGetPeriodicContStateRanges
#define rtmGetPeriodicContStateRanges(rtm) ((rtm)->periodicContStateRanges)
#endif

#ifndef rtmSetPeriodicContStateRanges
#define rtmSetPeriodicContStateRanges(rtm, val) ((rtm)->periodicContStateRanges = (val))
#endif

#ifndef rtmGetSampleHitArray
#define rtmGetSampleHitArray(rtm)      ((rtm)->Timing.sampleHitArray)
#endif

#ifndef rtmGetStepSize
#define rtmGetStepSize(rtm)            ((rtm)->Timing.stepSize)
#endif

#ifndef rtmGetZCCacheNeedsReset
#define rtmGetZCCacheNeedsReset(rtm)   ((rtm)->zCCacheNeedsReset)
#endif

#ifndef rtmSetZCCacheNeedsReset
#define rtmSetZCCacheNeedsReset(rtm, val) ((rtm)->zCCacheNeedsReset = (val))
#endif

#ifndef rtmGet_TimeOfLastOutput
#define rtmGet_TimeOfLastOutput(rtm)   ((rtm)->Timing.timeOfLastOutput)
#endif

#ifndef rtmGetdX
#define rtmGetdX(rtm)                  ((rtm)->derivs)
#endif

#ifndef rtmSetdX
#define rtmSetdX(rtm, val)             ((rtm)->derivs = (val))
#endif

#ifndef rtmCounterLimit
#define rtmCounterLimit(rtm, idx)      ((rtm)->Timing.TaskCounters.cLimit[(idx)])
#endif

#ifndef rtmGetErrorStatus
#define rtmGetErrorStatus(rtm)         ((rtm)->errorStatus)
#endif

#ifndef rtmSetErrorStatus
#define rtmSetErrorStatus(rtm, val)    ((rtm)->errorStatus = (val))
#endif

#ifndef rtmStepTask
#define rtmStepTask(rtm, idx)          ((rtm)->Timing.TaskCounters.TID[(idx)] == 0)
#endif

#ifndef rtmGetStopRequested
#define rtmGetStopRequested(rtm)       ((rtm)->Timing.stopRequestedFlag)
#endif

#ifndef rtmSetStopRequested
#define rtmSetStopRequested(rtm, val)  ((rtm)->Timing.stopRequestedFlag = (val))
#endif

#ifndef rtmGetStopRequestedPtr
#define rtmGetStopRequestedPtr(rtm)    (&((rtm)->Timing.stopRequestedFlag))
#endif

#ifndef rtmGetT
#define rtmGetT(rtm)                   (rtmGetTPtr((rtm))[0])
#endif

#ifndef rtmGetTFinal
#define rtmGetTFinal(rtm)              ((rtm)->Timing.tFinal)
#endif

#ifndef rtmGetTPtr
#define rtmGetTPtr(rtm)                ((rtm)->Timing.t)
#endif

#ifndef rtmGetTStart
#define rtmGetTStart(rtm)              ((rtm)->Timing.tStart)
#endif

#ifndef rtmTaskCounter
#define rtmTaskCounter(rtm, idx)       ((rtm)->Timing.TaskCounters.TID[(idx)])
#endif

#ifndef rtmGetTimeOfLastOutput
#define rtmGetTimeOfLastOutput(rtm)    ((rtm)->Timing.timeOfLastOutput)
#endif

/* Block signals (default storage) */
struct B_control_vectorial_T {
  real_T Encoder_o1;                   /* '<Root>/Encoder' */
  real_T Encoder_o2;                   /* '<Root>/Encoder' */
  real_T MultiportSwitch[2];           /* '<S5>/Multiport Switch' */
  real_T DataTypeConversion;           /* '<S1>/Data Type Conversion' */
  real_T Delay4;                       /* '<S1>/Delay4' */
  real_T Delay3;                       /* '<S1>/Delay3' */
  real_T Switch1;                      /* '<S1>/Switch1' */
  real_T Delay1;                       /* '<S1>/Delay1' */
  real_T Switch2;                      /* '<S1>/Switch2' */
  real_T CTEEncoder;                   /* '<S1>/CTE Encoder' */
  real_T Theta_r;                      /* '<S3>/p' */
  real_T Delay2;                       /* '<S1>/Delay2' */
  real_T Sum1;                         /* '<S1>/Sum1' */
  real_T GainVelocidad;                /* '<S1>/Gain Velocidad' */
  real_T p1;                           /* '<S3>/p1' */
  real_T uwb;                          /* '<S22>/1//wb' */
  real_T u;                            /* '<S29>/-1' */
  real_T TrigonometricFunction;        /* '<S28>/Trigonometric Function' */
  real_T Gain;                         /* '<S28>/Gain' */
  real_T TrigonometricFunction1;       /* '<S28>/Trigonometric Function1' */
  real_T TmpSignalConversionAtDotProduct[2];
  real_T FiltroPasaBaja;               /* '<S21>/Filtro Pasa Baja' */
  real_T FiltroPasaBaja1;              /* '<S21>/Filtro Pasa Baja1' */
  real_T Gain1;                        /* '<S27>/Gain1' */
  real_T FiltroPasaBaja2;              /* '<S21>/Filtro Pasa Baja2' */
  real_T Gain2;                        /* '<S27>/Gain2' */
  real_T Sum1_d;                       /* '<S27>/Sum1' */
  real_T Gain_b;                       /* '<S27>/Gain' */
  real_T Sum2;                         /* '<S27>/Sum2' */
  real_T Gain4;                        /* '<S27>/Gain4' */
  real_T TmpSignalConversionAtDotProdu_e[2];
  real_T DotProduct;                   /* '<S28>/Dot Product' */
  real_T iqiqn;                        /* '<S3>/iq->iqn' */
  real_T Divide5;                      /* '<S29>/Divide5' */
  real_T Conversion;                   /* '<S31>/Conversion' */
  real_T Abs1;                         /* '<S23>/Abs1' */
  real_T Saturation;                   /* '<S32>/Saturation' */
  real_T Product;                      /* '<S32>/Product' */
  real_T MinMax;                       /* '<S32>/MinMax' */
  real_T Vdcfactor;                    /* '<S32>/Vdc factor' */
  real_T Product1;                     /* '<S32>/Product1' */
  real_T Gain_n;                       /* '<Root>/Gain' */
  real_T Zerocancellationomega;        /* '<S25>/Zero-cancellation  omega' */
  real_T Sum;                          /* '<S25>/Sum' */
  real_T Kp;                           /* '<S39>/Kp' */
  real_T Ki;                           /* '<S39>/Ki' */
  real_T UnitDelay;                    /* '<S39>/Unit Delay' */
  real_T Kaw;                          /* '<S39>/Kaw' */
  real_T Sum1_g;                       /* '<S39>/Sum1' */
  real_T DiscreteTimeIntegrator;       /* '<S39>/Discrete-Time Integrator' */
  real_T Sum_o;                        /* '<S39>/Sum' */
  real_T Switch;                       /* '<S25>/Switch' */
  real_T SignChange;                   /* '<S32>/Sign Change' */
  real_T Switch_o;                     /* '<S33>/Switch' */
  real_T Switch2_e;                    /* '<S33>/Switch2' */
  real_T Switch_m[2];                  /* '<S23>/Switch' */
  real_T xr;                           /* '<S34>/x->r' */
  real_T xtheta;                       /* '<S34>/x->theta' */
  real_T Sum1_gv;                      /* '<S24>/Sum1' */
  real_T UnitDelay_g[2];               /* '<S3>/Unit Delay' */
  real_T vdqnvdq[2];                   /* '<S3>/vdqn-> vdq' */
  real_T MathFunction[2];              /* '<S35>/Math Function' */
  real_T SumofElements;                /* '<S35>/Sum of Elements' */
  real_T Sqrt;                         /* '<S35>/Sqrt' */
  real_T Switch_p;                     /* '<S37>/Switch' */
  real_T Product_c;                    /* '<S35>/Product' */
  real_T Sum_d;                        /* '<S24>/Sum' */
  real_T Gain_a;                       /* '<S24>/Gain' */
  real_T UnitDelay_o;                  /* '<S24>/Unit Delay' */
  real_T Gain1_k;                      /* '<S24>/Gain1' */
  real_T Sum4;                         /* '<S24>/Sum4' */
  real_T DiscreteTimeIntegrator_c;     /* '<S24>/Discrete-Time Integrator' */
  real_T Saturation_n;                 /* '<S24>/Saturation' */
  real_T Product_l;                    /* '<S24>/Product' */
  real_T Sum2_e;                       /* '<S24>/Sum2' */
  real_T rx;                           /* '<S36>/r->x' */
  real_T ididn1;                       /* '<S3>/id->idn1' */
  real_T TmpSignalConversionAtDotProdu_g[2];
  real_T DotProduct1;                  /* '<S28>/Dot Product1' */
  real_T ididn;                        /* '<S3>/id->idn' */
  real_T Sum_j;                        /* '<S29>/Sum' */
  real_T kp;                           /* '<S29>/kp' */
  real_T Integrator;                   /* '<S29>/Integrator' */
  real_T ki;                           /* '<S29>/ki' */
  real_T Sum1_k;                       /* '<S29>/Sum1' */
  real_T Sum2_m;                       /* '<S29>/Sum2' */
  real_T thetay;                       /* '<S36>/theta->y' */
  real_T iqiqn1;                       /* '<S3>/iq->iqn1' */
  real_T Sum4_f;                       /* '<S30>/Sum4' */
  real_T kp_h;                         /* '<S30>/kp' */
  real_T Integrator_h;                 /* '<S30>/Integrator' */
  real_T ki_g;                         /* '<S30>/ki' */
  real_T Sum1_i;                       /* '<S30>/Sum1' */
  real_T k_d;                          /* '<S30>/k' */
  real_T Divide5_l;                    /* '<S30>/Divide5' */
  real_T Sum2_i;                       /* '<S30>/Sum2' */
  real_T Sum3;                         /* '<S30>/Sum3' */
  real_T Switch_k[3];                  /* '<Root>/Switch' */
  real_T DigitalClock;                 /* '<S19>/Digital Clock' */
  real_T Add1;                         /* '<S19>/Add1' */
  real_T MathFunction_l;               /* '<S19>/Math Function' */
  real_T uib1;                         /* '<S19>/1\ib1' */
  real_T uDLookupTable;                /* '<S19>/1-D Lookup Table' */
  real_T Add3;                         /* '<S19>/Add3' */
  real_T Add3_g;                       /* '<S10>/Add3' */
  real_T Gain1_k2;                     /* '<S10>/Gain1' */
  real_T MUL1;                         /* '<S10>/MUL1' */
  real_T Add4;                         /* '<S10>/Add4' */
  real_T DataTypeConversion_b[6];      /* '<S2>/Data Type Conversion' */
  real_T Abs1_c;                       /* '<S1>/Abs1' */
  real_T Clock;                        /* '<S6>/Clock' */
  real_T Sum_ds;                       /* '<S6>/Sum' */
  real_T TmpRTBAtFiltroPasaBaja1Inport1;
  real_T TmpRTBAtFiltroPasaBaja2Inport1;
  real_T TmpRTBAtFiltroPasaBajaInport1;
  real_T Abs;                          /* '<S29>/Abs' */
  real_T Switch_h;                     /* '<S29>/Switch' */
  real_T Abs_e;                        /* '<S30>/Abs' */
  real_T Switch_e;                     /* '<S30>/Switch' */
  real_T Sum3_k;                       /* '<S24>/Sum3' */
  real_T Sum1_h;                       /* '<S25>/Sum1' */
  real_T CorrientesyPar_o1;            /* '<Root>/Corrientes y Par' */
  real_T CorrientesyPar_o2;            /* '<Root>/Corrientes y Par' */
  real_T CorrientesyPar_o3;            /* '<Root>/Corrientes y Par' */
  real_T TmpSignalConversionAtDotProd_ex[2];
  real_T TrigonometricFunction_a;      /* '<S41>/Trigonometric Function' */
  real_T Gain1_p;                      /* '<S41>/Gain1' */
  real_T TrigonometricFunction1_h;     /* '<S41>/Trigonometric Function1' */
  real_T TmpSignalConversionAtDotProd_gl[2];
  real_T DotProduct1_n;                /* '<S41>/Dot Product1' */
  real_T Gain1_i;                      /* '<S40>/Gain1' */
  real_T Gain2_e;                      /* '<S40>/Gain2' */
  real_T TmpSignalConversionAtDotProdu_j[2];
  real_T DotProduct_o;                 /* '<S41>/Dot Product' */
  real_T Gain_j;                       /* '<S40>/Gain' */
  real_T Sum_g;                        /* '<S40>/Sum' */
  real_T Gain3;                        /* '<S40>/Gain3' */
  real_T Sum1_ds;                      /* '<S40>/Sum1' */
  real_T Sum2_h;                       /* '<S25>/Sum2' */
  real_T Kv_w;                         /* '<S25>/Kv_w' */
  real_T radsrpm;                      /* '<S23>/rad//s->rpm' */
  real_T LookupTableidreference;       /* '<S23>/Lookup Table id reference' */
  real_T LookupTableiqreference;       /* '<S23>/Lookup Table iq reference' */
  real_T TqiqRef;                      /* '<S23>/Tq--> iqRef' */
  real_T Switch_a;                     /* '<S1>/Switch' */
  real_T Sum_a;                        /* '<S1>/Sum' */
  real_T Gain1_f;                      /* '<S1>/Gain1' */
  real_T In1;                          /* '<S9>/In1' */
  boolean_T DataTypeConversion2;       /* '<S5>/Data Type Conversion2' */
  boolean_T Memory;                    /* '<S5>/Memory' */
  boolean_T LogicalOperator1;          /* '<S5>/Logical Operator1' */
  boolean_T Compare;                   /* '<S38>/Compare' */
  boolean_T LowerRelop1;               /* '<S33>/LowerRelop1' */
  boolean_T UpperRelop;                /* '<S33>/UpperRelop' */
  boolean_T RelationalOperator2[3];    /* '<S14>/Relational Operator2' */
  boolean_T LogicalOperator4[3];       /* '<S2>/Logical Operator4' */
  boolean_T RelationalOperator;        /* '<S6>/Relational Operator' */
  boolean_T RelationalOperator1;       /* '<S8>/Relational Operator1' */
  boolean_T RelationalOperator1_m;     /* '<S7>/Relational Operator1' */
};

/* Block states (default storage) for system '<Root>' */
struct DW_control_vectorial_T {
  real_T Delay4_DSTATE;                /* '<S1>/Delay4' */
  real_T Delay3_DSTATE[200];           /* '<S1>/Delay3' */
  real_T Delay1_DSTATE;                /* '<S1>/Delay1' */
  real_T Delay2_DSTATE[200];           /* '<S1>/Delay2' */
  real_T UnitDelay_DSTATE;             /* '<S39>/Unit Delay' */
  real_T DiscreteTimeIntegrator_DSTATE;/* '<S39>/Discrete-Time Integrator' */
  real_T UnitDelay_DSTATE_j[2];        /* '<S3>/Unit Delay' */
  real_T UnitDelay_DSTATE_p;           /* '<S24>/Unit Delay' */
  real_T DiscreteTimeIntegrator_DSTATE_h;/* '<S24>/Discrete-Time Integrator' */
  real_T TmpRTBAtFiltroPasaBaja1Inport1_[2];/* synthesized block */
  real_T TmpRTBAtFiltroPasaBaja2Inport1_[2];/* synthesized block */
  real_T TmpRTBAtFiltroPasaBajaInport1_B[2];/* synthesized block */
  void *Encoder_PWORK[2];              /* '<Root>/Encoder' */
  void *Digitaloutput_PWORK[2];        /* '<Root>/Digital output' */
  struct {
    void *LoggedData[2];
  } Scope_PWORK;                       /* '<Root>/Scope' */

  struct {
    void *USERIO_P_IND;
    void *PROG_SPACE_P_IND;
    void *CONFIG_REGISTER_P_IND;
    void *CONDITIONING_MODULE_IO3xx_2x_P_IND;
    void *DEVICENAME_P_IND;
    void *DMA_CONTROLLER_P_IND;
  } Setup_PWORK;                       /* '<Root>/Setup' */

  void *CorrientesyPar_PWORK[3];       /* '<Root>/Corrientes y Par' */
  uint32_T m_bpIndex;                  /* '<S19>/1-D Lookup Table' */
  int_T Digitaloutput_IWORK;           /* '<Root>/Digital output' */
  struct {
    int_T MODULEARCHITECTURE_I_IND;
  } Setup_IWORK;                       /* '<Root>/Setup' */

  int8_T DiscreteTimeIntegrator_PrevRese;/* '<S39>/Discrete-Time Integrator' */
  int8_T TmpRTBAtFiltroPasaBaja1Inport_a;/* synthesized block */
  int8_T TmpRTBAtFiltroPasaBaja1Inport_j;/* synthesized block */
  int8_T TmpRTBAtFiltroPasaBaja2Inport_l;/* synthesized block */
  int8_T TmpRTBAtFiltroPasaBaja2Inport_p;/* synthesized block */
  int8_T TmpRTBAtFiltroPasaBajaInport1_R;/* synthesized block */
  int8_T TmpRTBAtFiltroPasaBajaInport1_W;/* synthesized block */
  int8_T POSITIVEEdge_SubsysRanBC;     /* '<S5>/POSITIVE Edge' */
  int8_T NEGATIVEEdge_SubsysRanBC;     /* '<S5>/NEGATIVE Edge' */
  int8_T TriggeredSubsystem_SubsysRanBC;/* '<S6>/Triggered Subsystem' */
  boolean_T Memory_PreviousInput;      /* '<S5>/Memory' */
  boolean_T POSITIVEEdge_MODE;         /* '<S5>/POSITIVE Edge' */
  boolean_T NEGATIVEEdge_MODE;         /* '<S5>/NEGATIVE Edge' */
};

/* Continuous states (default storage) */
struct X_control_vectorial_T {
  real_T FiltroPasaBaja_CSTATE;        /* '<S21>/Filtro Pasa Baja' */
  real_T FiltroPasaBaja1_CSTATE;       /* '<S21>/Filtro Pasa Baja1' */
  real_T FiltroPasaBaja2_CSTATE;       /* '<S21>/Filtro Pasa Baja2' */
  real_T Integrator_CSTATE;            /* '<S29>/Integrator' */
  real_T Integrator_CSTATE_k;          /* '<S30>/Integrator' */
};

/* State derivatives (default storage) */
struct XDot_control_vectorial_T {
  real_T FiltroPasaBaja_CSTATE;        /* '<S21>/Filtro Pasa Baja' */
  real_T FiltroPasaBaja1_CSTATE;       /* '<S21>/Filtro Pasa Baja1' */
  real_T FiltroPasaBaja2_CSTATE;       /* '<S21>/Filtro Pasa Baja2' */
  real_T Integrator_CSTATE;            /* '<S29>/Integrator' */
  real_T Integrator_CSTATE_k;          /* '<S30>/Integrator' */
};

/* State disabled  */
struct XDis_control_vectorial_T {
  boolean_T FiltroPasaBaja_CSTATE;     /* '<S21>/Filtro Pasa Baja' */
  boolean_T FiltroPasaBaja1_CSTATE;    /* '<S21>/Filtro Pasa Baja1' */
  boolean_T FiltroPasaBaja2_CSTATE;    /* '<S21>/Filtro Pasa Baja2' */
  boolean_T Integrator_CSTATE;         /* '<S29>/Integrator' */
  boolean_T Integrator_CSTATE_k;       /* '<S30>/Integrator' */
};

/* Zero-crossing (trigger) state */
struct PrevZCX_control_vectorial_T {
  ZCSigState TriggeredSubsystem_Trig_ZCE;/* '<S6>/Triggered Subsystem' */
};

#ifndef ODE3_INTG
#define ODE3_INTG

/* ODE3 Integration Data */
struct ODE3_IntgData {
  real_T *y;                           /* output */
  real_T *f[3];                        /* derivatives */
};

#endif

/* Real-time Model Data Structure */
struct tag_RTM_control_vectorial_T {
  struct SimStruct_tag * *childSfunctions;
  const char_T *errorStatus;
  SS_SimMode simMode;
  RTWSolverInfo solverInfo;
  RTWSolverInfo *solverInfoPtr;
  void *sfcnInfo;

  /*
   * NonInlinedSFcns:
   * The following substructure contains information regarding
   * non-inlined s-functions used in the model.
   */
  struct {
    RTWSfcnInfo sfcnInfo;
    time_T *taskTimePtrs[3];
    SimStruct childSFunctions[3];
    SimStruct *childSFunctionPtrs[3];
    struct _ssBlkInfo2 blkInfo2[3];
    struct _ssSFcnModelMethods2 methods2[3];
    struct _ssSFcnModelMethods3 methods3[3];
    struct _ssSFcnModelMethods4 methods4[3];
    struct _ssStatesInfo2 statesInfo2[3];
    ssPeriodicStatesInfo periodicStatesInfo[3];
    struct _ssPortInfo2 inputOutputPortInfo2[3];
    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortOutputs outputPortInfo[2];
      struct _ssOutPortUnit outputPortUnits[2];
      struct _ssOutPortCoSimAttribute outputPortCoSimAttribute[2];
      uint_T attribs[4];
      mxArray *params[4];
      struct _ssDWorkRecord dWork[1];
      struct _ssDWorkAuxRecord dWorkAux[1];
    } Sfcn0;

    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortInputs inputPortInfo[6];
      struct _ssInPortUnit inputPortUnits[6];
      struct _ssInPortCoSimAttribute inputPortCoSimAttribute[6];
      uint_T attribs[6];
      mxArray *params[6];
      struct _ssDWorkRecord dWork[2];
      struct _ssDWorkAuxRecord dWorkAux[2];
    } Sfcn1;

    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortOutputs outputPortInfo[3];
      struct _ssOutPortUnit outputPortUnits[3];
      struct _ssOutPortCoSimAttribute outputPortCoSimAttribute[3];
      uint_T attribs[9];
      mxArray *params[9];
      struct _ssDWorkRecord dWork[1];
      struct _ssDWorkAuxRecord dWorkAux[1];
    } Sfcn2;
  } NonInlinedSFcns;

  X_control_vectorial_T *contStates;
  int_T *periodicContStateIndices;
  real_T *periodicContStateRanges;
  real_T *derivs;
  XDis_control_vectorial_T *contStateDisabled;
  boolean_T zCCacheNeedsReset;
  boolean_T derivCacheNeedsReset;
  boolean_T CTOutputIncnstWithState;
  real_T odeY[5];
  real_T odeF[3][5];
  ODE3_IntgData intgData;

  /*
   * Sizes:
   * The following substructure contains sizes information
   * for many of the model attributes such as inputs, outputs,
   * dwork, sample times, etc.
   */
  struct {
    uint32_T options;
    int_T numContStates;
    int_T numPeriodicContStates;
    int_T numU;
    int_T numY;
    int_T numSampTimes;
    int_T numBlocks;
    int_T numBlockIO;
    int_T numBlockPrms;
    int_T numDwork;
    int_T numSFcnPrms;
    int_T numSFcns;
    int_T numIports;
    int_T numOports;
    int_T numNonSampZCs;
    int_T sysDirFeedThru;
    int_T rtwGenSfcn;
  } Sizes;

  /*
   * Timing:
   * The following substructure contains information regarding
   * the timing information for the model.
   */
  struct {
    time_T stepSize;
    uint32_T clockTick0;
    uint32_T clockTickH0;
    time_T stepSize0;
    uint32_T clockTick1;
    uint32_T clockTickH1;
    time_T stepSize1;
    uint32_T clockTick2;
    uint32_T clockTickH2;
    time_T stepSize2;
    struct {
      uint8_T TID[3];
      uint8_T cLimit[3];
    } TaskCounters;

    struct {
      uint8_T TID1_2;
    } RateInteraction;

    time_T tStart;
    time_T tFinal;
    time_T timeOfLastOutput;
    SimTimeStep simTimeStep;
    boolean_T stopRequestedFlag;
    time_T *sampleTimes;
    time_T *offsetTimes;
    int_T *sampleTimeTaskIDPtr;
    int_T *sampleHits;
    int_T *perTaskSampleHits;
    time_T *t;
    time_T sampleTimesArray[3];
    time_T offsetTimesArray[3];
    int_T sampleTimeTaskIDArray[3];
    int_T sampleHitArray[3];
    int_T perTaskSampleHitsArray[9];
    time_T tArray[3];
  } Timing;
};

/* Block signals (default storage) */
#ifdef __cplusplus

extern "C"
{

#endif

  extern struct B_control_vectorial_T control_vectorial_B;

#ifdef __cplusplus

}

#endif

/* Continuous states (default storage) */
extern X_control_vectorial_T control_vectorial_X;

/* Disabled states (default storage) */
extern XDis_control_vectorial_T control_vectorial_XDis;

/* Block states (default storage) */
extern struct DW_control_vectorial_T control_vectorial_DW;

/* Zero-crossing (trigger) state */
extern PrevZCX_control_vectorial_T control_vectorial_PrevZCX;

#ifdef __cplusplus

extern "C"
{

#endif

  /* Model entry point functions */
  extern void control_vectorial_initialize(void);
  extern void control_vectorial_step0(void);
  extern void control_vectorial_step2(void);/* Sample time: [0.0001s, 0.0s] */
  extern void control_vectorial_terminate(void);

#ifdef __cplusplus

}

#endif

/* Real-time Model object */
#ifdef __cplusplus

extern "C"
{

#endif

  extern RT_MODEL_control_vectorial_T *const control_vectorial_M;

#ifdef __cplusplus

}

#endif

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'control_vectorial'
 * '<S1>'   : 'control_vectorial/Decodificador'
 * '<S2>'   : 'control_vectorial/PWM Generator (2-Level)'
 * '<S3>'   : 'control_vectorial/Speed FO control'
 * '<S4>'   : 'control_vectorial/Decodificador/Edge Detector'
 * '<S5>'   : 'control_vectorial/Decodificador/Edge Detector/Model'
 * '<S6>'   : 'control_vectorial/Decodificador/Edge Detector/Model/Internal dirac generator'
 * '<S7>'   : 'control_vectorial/Decodificador/Edge Detector/Model/NEGATIVE Edge'
 * '<S8>'   : 'control_vectorial/Decodificador/Edge Detector/Model/POSITIVE Edge'
 * '<S9>'   : 'control_vectorial/Decodificador/Edge Detector/Model/Internal dirac generator/Triggered Subsystem'
 * '<S10>'  : 'control_vectorial/PWM Generator (2-Level)/Cr_MinMax'
 * '<S11>'  : 'control_vectorial/PWM Generator (2-Level)/Modulator type'
 * '<S12>'  : 'control_vectorial/PWM Generator (2-Level)/Reference signal'
 * '<S13>'  : 'control_vectorial/PWM Generator (2-Level)/Sampling'
 * '<S14>'  : 'control_vectorial/PWM Generator (2-Level)/Modulator type/One Three Phase Bridge'
 * '<S15>'  : 'control_vectorial/PWM Generator (2-Level)/Reference signal/External'
 * '<S16>'  : 'control_vectorial/PWM Generator (2-Level)/Sampling/Unsync Natural'
 * '<S17>'  : 'control_vectorial/PWM Generator (2-Level)/Sampling/Unsync Natural/Unsync_NaturalSampling'
 * '<S18>'  : 'control_vectorial/PWM Generator (2-Level)/Sampling/Unsync Natural/Unsync_NaturalSampling/Triangle Generator'
 * '<S19>'  : 'control_vectorial/PWM Generator (2-Level)/Sampling/Unsync Natural/Unsync_NaturalSampling/Triangle Generator/Model'
 * '<S20>'  : 'control_vectorial/Speed FO control/ABC->dq coordinate transform'
 * '<S21>'  : 'control_vectorial/Speed FO control/Current first order filters'
 * '<S22>'  : 'control_vectorial/Speed FO control/Current_loops'
 * '<S23>'  : 'control_vectorial/Speed FO control/PMSM Current Reference Generator'
 * '<S24>'  : 'control_vectorial/Speed FO control/PMSM Field-Weakening Controller1'
 * '<S25>'  : 'control_vectorial/Speed FO control/Velocity Controller'
 * '<S26>'  : 'control_vectorial/Speed FO control/dq->ABC coordinate transform'
 * '<S27>'  : 'control_vectorial/Speed FO control/ABC->dq coordinate transform/ABC_DQ corrientes'
 * '<S28>'  : 'control_vectorial/Speed FO control/ABC->dq coordinate transform/DQ->dq'
 * '<S29>'  : 'control_vectorial/Speed FO control/Current_loops/PI_Idn'
 * '<S30>'  : 'control_vectorial/Speed FO control/Current_loops/PI_Iqn'
 * '<S31>'  : 'control_vectorial/Speed FO control/PMSM Current Reference Generator/Data Type Conversion Inherited2'
 * '<S32>'  : 'control_vectorial/Speed FO control/PMSM Current Reference Generator/Torque limiter'
 * '<S33>'  : 'control_vectorial/Speed FO control/PMSM Current Reference Generator/Torque limiter/Tq saturation'
 * '<S34>'  : 'control_vectorial/Speed FO control/PMSM Field-Weakening Controller1/Cartesian to Polar'
 * '<S35>'  : 'control_vectorial/Speed FO control/PMSM Field-Weakening Controller1/Modulation index'
 * '<S36>'  : 'control_vectorial/Speed FO control/PMSM Field-Weakening Controller1/Polar to Cartesian'
 * '<S37>'  : 'control_vectorial/Speed FO control/PMSM Field-Weakening Controller1/Modulation index/Prevent division by 0'
 * '<S38>'  : 'control_vectorial/Speed FO control/Velocity Controller/Compare To Constant'
 * '<S39>'  : 'control_vectorial/Speed FO control/Velocity Controller/Discrete PI Controller'
 * '<S40>'  : 'control_vectorial/Speed FO control/dq->ABC coordinate transform/DQ_ABC'
 * '<S41>'  : 'control_vectorial/Speed FO control/dq->ABC coordinate transform/dq->DQ'
 */
#endif                                 /* control_vectorial_h_ */
