/*
 * control_Velocidad.h
 *
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * Code generation for model "control_Velocidad".
 *
 * Model version              : 1.53
 * Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
 * C++ source code generated on : Fri Aug 22 13:33:37 2025
 *
 * Target selection: speedgoat.tlc
 * Note: GRT includes extra infrastructure and instrumentation for prototyping
 * Embedded hardware selection: Intel->x86-64 (Linux 64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#ifndef control_Velocidad_h_
#define control_Velocidad_h_
#include "rtwtypes.h"
#include "simstruc.h"
#include "fixedpoint.h"
#include "sg_fpga_io30x_setup_util.h"
#include "sg_fpga_io31x_io32x_setup_util.h"
#include "sg_fpga_io33x_setup_util.h"
#include "sg_fpga_io36x_setup_util.h"
#include "sg_fpga_io39x_setup_util.h"
#include "sg_fpga_io3xx_scatter_gather_dma.h"
#include "sg_fpga_nigora_setup_util.h"
#include "sg_common.h"
#include "sg_printf.h"
#include "control_Velocidad_types.h"
#include <stddef.h>

extern "C"
{

#include "rtGetNaN.h"

}

#include <cstring>
#include "control_Velocidad_cal.h"

extern "C"
{

#include "rt_nonfinite.h"

}

#include "zero_crossing_types.h"

/* Macros for accessing real-time model data structure */
#ifndef rtmGetContStateDisabled
#define rtmGetContStateDisabled(rtm)   ((rtm)->contStateDisabled)
#endif

#ifndef rtmSetContStateDisabled
#define rtmSetContStateDisabled(rtm, val) ((rtm)->contStateDisabled = (val))
#endif

#ifndef rtmGetContStates
#define rtmGetContStates(rtm)          ((rtm)->contStates)
#endif

#ifndef rtmSetContStates
#define rtmSetContStates(rtm, val)     ((rtm)->contStates = (val))
#endif

#ifndef rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag
#define rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm) ((rtm)->CTOutputIncnstWithState)
#endif

#ifndef rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag
#define rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm, val) ((rtm)->CTOutputIncnstWithState = (val))
#endif

#ifndef rtmGetDerivCacheNeedsReset
#define rtmGetDerivCacheNeedsReset(rtm) ((rtm)->derivCacheNeedsReset)
#endif

#ifndef rtmSetDerivCacheNeedsReset
#define rtmSetDerivCacheNeedsReset(rtm, val) ((rtm)->derivCacheNeedsReset = (val))
#endif

#ifndef rtmGetFinalTime
#define rtmGetFinalTime(rtm)           ((rtm)->Timing.tFinal)
#endif

#ifndef rtmGetIntgData
#define rtmGetIntgData(rtm)            ((rtm)->intgData)
#endif

#ifndef rtmSetIntgData
#define rtmSetIntgData(rtm, val)       ((rtm)->intgData = (val))
#endif

#ifndef rtmGetOdeF
#define rtmGetOdeF(rtm)                ((rtm)->odeF)
#endif

#ifndef rtmSetOdeF
#define rtmSetOdeF(rtm, val)           ((rtm)->odeF = (val))
#endif

#ifndef rtmGetOdeY
#define rtmGetOdeY(rtm)                ((rtm)->odeY)
#endif

#ifndef rtmSetOdeY
#define rtmSetOdeY(rtm, val)           ((rtm)->odeY = (val))
#endif

#ifndef rtmGetPeriodicContStateIndices
#define rtmGetPeriodicContStateIndices(rtm) ((rtm)->periodicContStateIndices)
#endif

#ifndef rtmSetPeriodicContStateIndices
#define rtmSetPeriodicContStateIndices(rtm, val) ((rtm)->periodicContStateIndices = (val))
#endif

#ifndef rtmGetPeriodicContStateRanges
#define rtmGetPeriodicContStateRanges(rtm) ((rtm)->periodicContStateRanges)
#endif

#ifndef rtmSetPeriodicContStateRanges
#define rtmSetPeriodicContStateRanges(rtm, val) ((rtm)->periodicContStateRanges = (val))
#endif

#ifndef rtmGetSampleHitArray
#define rtmGetSampleHitArray(rtm)      ((rtm)->Timing.sampleHitArray)
#endif

#ifndef rtmGetStepSize
#define rtmGetStepSize(rtm)            ((rtm)->Timing.stepSize)
#endif

#ifndef rtmGetZCCacheNeedsReset
#define rtmGetZCCacheNeedsReset(rtm)   ((rtm)->zCCacheNeedsReset)
#endif

#ifndef rtmSetZCCacheNeedsReset
#define rtmSetZCCacheNeedsReset(rtm, val) ((rtm)->zCCacheNeedsReset = (val))
#endif

#ifndef rtmGet_TimeOfLastOutput
#define rtmGet_TimeOfLastOutput(rtm)   ((rtm)->Timing.timeOfLastOutput)
#endif

#ifndef rtmGetdX
#define rtmGetdX(rtm)                  ((rtm)->derivs)
#endif

#ifndef rtmSetdX
#define rtmSetdX(rtm, val)             ((rtm)->derivs = (val))
#endif

#ifndef rtmGetErrorStatus
#define rtmGetErrorStatus(rtm)         ((rtm)->errorStatus)
#endif

#ifndef rtmSetErrorStatus
#define rtmSetErrorStatus(rtm, val)    ((rtm)->errorStatus = (val))
#endif

#ifndef rtmGetStopRequested
#define rtmGetStopRequested(rtm)       ((rtm)->Timing.stopRequestedFlag)
#endif

#ifndef rtmSetStopRequested
#define rtmSetStopRequested(rtm, val)  ((rtm)->Timing.stopRequestedFlag = (val))
#endif

#ifndef rtmGetStopRequestedPtr
#define rtmGetStopRequestedPtr(rtm)    (&((rtm)->Timing.stopRequestedFlag))
#endif

#ifndef rtmGetT
#define rtmGetT(rtm)                   (rtmGetTPtr((rtm))[0])
#endif

#ifndef rtmGetTFinal
#define rtmGetTFinal(rtm)              ((rtm)->Timing.tFinal)
#endif

#ifndef rtmGetTPtr
#define rtmGetTPtr(rtm)                ((rtm)->Timing.t)
#endif

#ifndef rtmGetTStart
#define rtmGetTStart(rtm)              ((rtm)->Timing.tStart)
#endif

#ifndef rtmGetTimeOfLastOutput
#define rtmGetTimeOfLastOutput(rtm)    ((rtm)->Timing.timeOfLastOutput)
#endif

/* Block signals (default storage) */
struct B_control_Velocidad_T {
  real_T Gain1;                        /* '<Root>/Gain1' */
  real_T Abs;                          /* '<Root>/Abs' */
  real_T CTE_amplitud;                 /* '<Root>/CTE_amplitud' */
  real_T Saturation;                   /* '<Root>/Saturation' */
  real_T DiscreteTimeIntegrator;       /* '<S2>/Discrete-Time Integrator' */
  real_T TrigonometricFunction;        /* '<S2>/Trigonometric Function' */
  real_T Sum;                          /* '<S2>/Sum' */
  real_T TrigonometricFunction1;       /* '<S2>/Trigonometric Function1' */
  real_T Sum1;                         /* '<S2>/Sum1' */
  real_T TrigonometricFunction2;       /* '<S2>/Trigonometric Function2' */
  real_T Product[3];                   /* '<Root>/Product' */
  real_T DigitalClock;                 /* '<S11>/Digital Clock' */
  real_T Add1;                         /* '<S11>/Add1' */
  real_T MathFunction;                 /* '<S11>/Math Function' */
  real_T uib1;                         /* '<S11>/1\ib1' */
  real_T Fcn;                          /* '<S11>/Fcn' */
  real_T CastToDouble[6];              /* '<S3>/Cast To Double' */
  real_T Gain;                         /* '<S2>/Gain' */
  real_T Digitalinput_o1;              /* '<Root>/Digital input' */
  real_T Digitalinput_o2;              /* '<Root>/Digital input' */
  real_T MultiportSwitch[2];           /* '<S5>/Multiport Switch' */
  real_T DataTypeConversion;           /* '<S1>/Data Type Conversion' */
  real_T Delay3;                       /* '<S1>/Delay3' */
  real_T Switch;                       /* '<S1>/Switch' */
  real_T Delay1;                       /* '<S1>/Delay1' */
  real_T Sum_l;                        /* '<S1>/Sum' */
  real_T CTEEncoder;                   /* '<S1>/CTE Encoder' */
  real_T FiltroPasaBaja;               /* '<S1>/Filtro Pasa Baja' */
  real_T Abs1;                         /* '<S1>/Abs1' */
  real_T Delay;                        /* '<S1>/Delay' */
  real_T Clock;                        /* '<S6>/Clock' */
  real_T Sum_g;                        /* '<S6>/Sum' */
  real_T Sum1_c;                       /* '<S1>/Sum1' */
  real_T Gain_e;                       /* '<S1>/Gain' */
  real_T Gain1_h;                      /* '<S1>/Gain1' */
  real_T In1;                          /* '<S9>/In1' */
  boolean_T RelationalOperator[3];     /* '<S3>/Relational Operator' */
  boolean_T LogicalOperator;           /* '<S3>/Logical Operator' */
  boolean_T LogicalOperator1;          /* '<S3>/Logical Operator1' */
  boolean_T LogicalOperator2;          /* '<S3>/Logical Operator2' */
  boolean_T DataTypeConversion2;       /* '<S5>/Data Type Conversion2' */
  boolean_T Memory;                    /* '<S5>/Memory' */
  boolean_T LogicalOperator1_g;        /* '<S5>/Logical Operator1' */
  boolean_T Delay4;                    /* '<S1>/Delay4' */
  boolean_T Switch1;                   /* '<S1>/Switch1' */
  boolean_T RelationalOperator_k;      /* '<S6>/Relational Operator' */
  boolean_T LogicalOperator_g;         /* '<S1>/Logical Operator' */
  boolean_T RelationalOperator1;       /* '<S8>/Relational Operator1' */
  boolean_T RelationalOperator1_e;     /* '<S7>/Relational Operator1' */
};

/* Block states (default storage) for system '<Root>' */
struct DW_control_Velocidad_T {
  real_T DiscreteTimeIntegrator_DSTATE;/* '<S2>/Discrete-Time Integrator' */
  real_T Delay3_DSTATE[100];           /* '<S1>/Delay3' */
  real_T Delay1_DSTATE;                /* '<S1>/Delay1' */
  real_T Delay_DSTATE[100];            /* '<S1>/Delay' */
  void *Digitaloutput_PWORK[2];        /* '<Root>/Digital output' */
  void *Digitalinput_PWORK[2];         /* '<Root>/Digital input' */
  struct {
    void *LoggedData[2];
  } Scope_PWORK;                       /* '<Root>/Scope' */

  struct {
    void *USERIO_P_IND;
    void *PROG_SPACE_P_IND;
    void *CONFIG_REGISTER_P_IND;
    void *CONDITIONING_MODULE_IO3xx_2x_P_IND;
    void *DEVICENAME_P_IND;
    void *DMA_CONTROLLER_P_IND;
  } Setup_PWORK;                       /* '<Root>/Setup' */

  int_T Digitaloutput_IWORK;           /* '<Root>/Digital output' */
  struct {
    int_T MODULEARCHITECTURE_I_IND;
  } Setup_IWORK;                       /* '<Root>/Setup' */

  boolean_T Delay4_DSTATE;             /* '<S1>/Delay4' */
  int8_T POSITIVEEdge_SubsysRanBC;     /* '<S5>/POSITIVE Edge' */
  int8_T NEGATIVEEdge_SubsysRanBC;     /* '<S5>/NEGATIVE Edge' */
  int8_T TriggeredSubsystem_SubsysRanBC;/* '<S6>/Triggered Subsystem' */
  boolean_T Memory_PreviousInput;      /* '<S5>/Memory' */
  boolean_T POSITIVEEdge_MODE;         /* '<S5>/POSITIVE Edge' */
  boolean_T NEGATIVEEdge_MODE;         /* '<S5>/NEGATIVE Edge' */
};

/* Continuous states (default storage) */
struct X_control_Velocidad_T {
  real_T FiltroPasaBaja_CSTATE;        /* '<S1>/Filtro Pasa Baja' */
};

/* State derivatives (default storage) */
struct XDot_control_Velocidad_T {
  real_T FiltroPasaBaja_CSTATE;        /* '<S1>/Filtro Pasa Baja' */
};

/* State disabled  */
struct XDis_control_Velocidad_T {
  boolean_T FiltroPasaBaja_CSTATE;     /* '<S1>/Filtro Pasa Baja' */
};

/* Zero-crossing (trigger) state */
struct PrevZCX_control_Velocidad_T {
  ZCSigState TriggeredSubsystem_Trig_ZCE;/* '<S6>/Triggered Subsystem' */
};

#ifndef ODE3_INTG
#define ODE3_INTG

/* ODE3 Integration Data */
struct ODE3_IntgData {
  real_T *y;                           /* output */
  real_T *f[3];                        /* derivatives */
};

#endif

/* Real-time Model Data Structure */
struct tag_RTM_control_Velocidad_T {
  struct SimStruct_tag * *childSfunctions;
  const char_T *errorStatus;
  SS_SimMode simMode;
  RTWSolverInfo solverInfo;
  RTWSolverInfo *solverInfoPtr;
  void *sfcnInfo;

  /*
   * NonInlinedSFcns:
   * The following substructure contains information regarding
   * non-inlined s-functions used in the model.
   */
  struct {
    RTWSfcnInfo sfcnInfo;
    time_T *taskTimePtrs[2];
    SimStruct childSFunctions[2];
    SimStruct *childSFunctionPtrs[2];
    struct _ssBlkInfo2 blkInfo2[2];
    struct _ssSFcnModelMethods2 methods2[2];
    struct _ssSFcnModelMethods3 methods3[2];
    struct _ssSFcnModelMethods4 methods4[2];
    struct _ssStatesInfo2 statesInfo2[2];
    ssPeriodicStatesInfo periodicStatesInfo[2];
    struct _ssPortInfo2 inputOutputPortInfo2[2];
    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortInputs inputPortInfo[6];
      struct _ssInPortUnit inputPortUnits[6];
      struct _ssInPortCoSimAttribute inputPortCoSimAttribute[6];
      uint_T attribs[6];
      mxArray *params[6];
      struct _ssDWorkRecord dWork[2];
      struct _ssDWorkAuxRecord dWorkAux[2];
    } Sfcn0;

    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortOutputs outputPortInfo[2];
      struct _ssOutPortUnit outputPortUnits[2];
      struct _ssOutPortCoSimAttribute outputPortCoSimAttribute[2];
      uint_T attribs[4];
      mxArray *params[4];
      struct _ssDWorkRecord dWork[1];
      struct _ssDWorkAuxRecord dWorkAux[1];
    } Sfcn1;
  } NonInlinedSFcns;

  X_control_Velocidad_T *contStates;
  int_T *periodicContStateIndices;
  real_T *periodicContStateRanges;
  real_T *derivs;
  XDis_control_Velocidad_T *contStateDisabled;
  boolean_T zCCacheNeedsReset;
  boolean_T derivCacheNeedsReset;
  boolean_T CTOutputIncnstWithState;
  real_T odeY[1];
  real_T odeF[3][1];
  ODE3_IntgData intgData;

  /*
   * Sizes:
   * The following substructure contains sizes information
   * for many of the model attributes such as inputs, outputs,
   * dwork, sample times, etc.
   */
  struct {
    uint32_T options;
    int_T numContStates;
    int_T numPeriodicContStates;
    int_T numU;
    int_T numY;
    int_T numSampTimes;
    int_T numBlocks;
    int_T numBlockIO;
    int_T numBlockPrms;
    int_T numDwork;
    int_T numSFcnPrms;
    int_T numSFcns;
    int_T numIports;
    int_T numOports;
    int_T numNonSampZCs;
    int_T sysDirFeedThru;
    int_T rtwGenSfcn;
  } Sizes;

  /*
   * Timing:
   * The following substructure contains information regarding
   * the timing information for the model.
   */
  struct {
    time_T stepSize;
    uint32_T clockTick0;
    uint32_T clockTickH0;
    time_T stepSize0;
    uint32_T clockTick1;
    uint32_T clockTickH1;
    time_T stepSize1;
    time_T tStart;
    time_T tFinal;
    time_T timeOfLastOutput;
    SimTimeStep simTimeStep;
    boolean_T stopRequestedFlag;
    time_T *sampleTimes;
    time_T *offsetTimes;
    int_T *sampleTimeTaskIDPtr;
    int_T *sampleHits;
    int_T *perTaskSampleHits;
    time_T *t;
    time_T sampleTimesArray[2];
    time_T offsetTimesArray[2];
    int_T sampleTimeTaskIDArray[2];
    int_T sampleHitArray[2];
    int_T perTaskSampleHitsArray[4];
    time_T tArray[2];
  } Timing;
};

/* Block signals (default storage) */
#ifdef __cplusplus

extern "C"
{

#endif

  extern struct B_control_Velocidad_T control_Velocidad_B;

#ifdef __cplusplus

}

#endif

/* Continuous states (default storage) */
extern X_control_Velocidad_T control_Velocidad_X;

/* Disabled states (default storage) */
extern XDis_control_Velocidad_T control_Velocidad_XDis;

/* Block states (default storage) */
extern struct DW_control_Velocidad_T control_Velocidad_DW;

/* Zero-crossing (trigger) state */
extern PrevZCX_control_Velocidad_T control_Velocidad_PrevZCX;

#ifdef __cplusplus

extern "C"
{

#endif

  /* Model entry point functions */
  extern void control_Velocidad_initialize(void);
  extern void control_Velocidad_step(void);
  extern void control_Velocidad_terminate(void);

#ifdef __cplusplus

}

#endif

/* Real-time Model object */
#ifdef __cplusplus

extern "C"
{

#endif

  extern RT_MODEL_control_Velocidad_T *const control_Velocidad_M;

#ifdef __cplusplus

}

#endif

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'control_Velocidad'
 * '<S1>'   : 'control_Velocidad/Decodificador'
 * '<S2>'   : 'control_Velocidad/Generador Trifasica Unitario'
 * '<S3>'   : 'control_Velocidad/Subsystem'
 * '<S4>'   : 'control_Velocidad/Decodificador/Edge Detector'
 * '<S5>'   : 'control_Velocidad/Decodificador/Edge Detector/Model'
 * '<S6>'   : 'control_Velocidad/Decodificador/Edge Detector/Model/Internal dirac generator'
 * '<S7>'   : 'control_Velocidad/Decodificador/Edge Detector/Model/NEGATIVE Edge'
 * '<S8>'   : 'control_Velocidad/Decodificador/Edge Detector/Model/POSITIVE Edge'
 * '<S9>'   : 'control_Velocidad/Decodificador/Edge Detector/Model/Internal dirac generator/Triggered Subsystem'
 * '<S10>'  : 'control_Velocidad/Subsystem/Sawtooth Generator'
 * '<S11>'  : 'control_Velocidad/Subsystem/Sawtooth Generator/Model'
 */
#endif                                 /* control_Velocidad_h_ */
