/*
 * ArranqueVF.cpp
 *
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * Code generation for model "ArranqueVF".
 *
 * Model version              : 1.13
 * Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
 * C++ source code generated on : Tue Jun  3 11:16:51 2025
 *
 * Target selection: speedgoat.tlc
 * Note: GRT includes extra infrastructure and instrumentation for prototyping
 * Embedded hardware selection: Intel->x86-64 (Linux 64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#include "ArranqueVF.h"
#include "ArranqueVF_cal.h"
#include "rtwtypes.h"
#include "ArranqueVF_private.h"
#include <cstring>

extern "C"
{

#include "rt_nonfinite.h"

}

const real_T ArranqueVF_RGND = 0.0;    /* real_T ground */

/* Block signals (default storage) */
B_ArranqueVF_T ArranqueVF_B;

/* Block states (default storage) */
DW_ArranqueVF_T ArranqueVF_DW;

/* Real-time model */
RT_MODEL_ArranqueVF_T ArranqueVF_M_ = RT_MODEL_ArranqueVF_T();
RT_MODEL_ArranqueVF_T *const ArranqueVF_M = &ArranqueVF_M_;

/* Model step function */
void ArranqueVF_step(void)
{
  /* Constant: '<Root>/Constant' */
  ArranqueVF_B.Constant = ArranqueVF_cal->Constant_Value;

  /* S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output1' */

  /* Level2 S-Function Block: '<Root>/Digital output1' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = ArranqueVF_M->childSfunctions[0];
    sfcnOutputs(rts,0);
  }

  /* S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */

  /* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = ArranqueVF_M->childSfunctions[1];
    sfcnOutputs(rts,0);
  }

  /* user code (Output function Trailer) */
  {
  }

  /* Update absolute time for base rate */
  /* The "clockTick0" counts the number of times the code of this task has
   * been executed. The absolute time is the multiplication of "clockTick0"
   * and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
   * overflow during the application lifespan selected.
   * Timer of this task consists of two 32 bit unsigned integers.
   * The two integers represent the low bits Timing.clockTick0 and the high bits
   * Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
   */
  if (!(++ArranqueVF_M->Timing.clockTick0)) {
    ++ArranqueVF_M->Timing.clockTickH0;
  }

  ArranqueVF_M->Timing.t[0] = ArranqueVF_M->Timing.clockTick0 *
    ArranqueVF_M->Timing.stepSize0 + ArranqueVF_M->Timing.clockTickH0 *
    ArranqueVF_M->Timing.stepSize0 * 4294967296.0;
}

/* Model initialize function */
void ArranqueVF_initialize(void)
{
  /* Registration code */

  /* initialize non-finites */
  rt_InitInfAndNaN(sizeof(real_T));
  rtsiSetSolverName(&ArranqueVF_M->solverInfo,"FixedStepDiscrete");
  ArranqueVF_M->solverInfoPtr = (&ArranqueVF_M->solverInfo);

  /* Initialize timing info */
  {
    int_T *mdlTsMap = ArranqueVF_M->Timing.sampleTimeTaskIDArray;
    mdlTsMap[0] = 0;
    ArranqueVF_M->Timing.sampleTimeTaskIDPtr = (&mdlTsMap[0]);
    ArranqueVF_M->Timing.sampleTimes = (&ArranqueVF_M->Timing.sampleTimesArray[0]);
    ArranqueVF_M->Timing.offsetTimes = (&ArranqueVF_M->Timing.offsetTimesArray[0]);

    /* task periods */
    ArranqueVF_M->Timing.sampleTimes[0] = (0.0001);

    /* task offsets */
    ArranqueVF_M->Timing.offsetTimes[0] = (0.0);
  }

  rtmSetTPtr(ArranqueVF_M, &ArranqueVF_M->Timing.tArray[0]);

  {
    int_T *mdlSampleHits = ArranqueVF_M->Timing.sampleHitArray;
    mdlSampleHits[0] = 1;
    ArranqueVF_M->Timing.sampleHits = (&mdlSampleHits[0]);
  }

  rtmSetTFinal(ArranqueVF_M, -1);
  ArranqueVF_M->Timing.stepSize0 = 0.0001;
  ArranqueVF_M->solverInfoPtr = (&ArranqueVF_M->solverInfo);
  ArranqueVF_M->Timing.stepSize = (0.0001);
  rtsiSetFixedStepSize(&ArranqueVF_M->solverInfo, 0.0001);
  rtsiSetSolverMode(&ArranqueVF_M->solverInfo, SOLVER_MODE_SINGLETASKING);

  /* block I/O */
  (void) std::memset((static_cast<void *>(&ArranqueVF_B)), 0,
                     sizeof(B_ArranqueVF_T));

  /* states (dwork) */
  (void) std::memset(static_cast<void *>(&ArranqueVF_DW), 0,
                     sizeof(DW_ArranqueVF_T));

  /* child S-Function registration */
  {
    RTWSfcnInfo *sfcnInfo = &ArranqueVF_M->NonInlinedSFcns.sfcnInfo;
    ArranqueVF_M->sfcnInfo = (sfcnInfo);
    rtssSetErrorStatusPtr(sfcnInfo, (&rtmGetErrorStatus(ArranqueVF_M)));
    ArranqueVF_M->Sizes.numSampTimes = (1);
    rtssSetNumRootSampTimesPtr(sfcnInfo, &ArranqueVF_M->Sizes.numSampTimes);
    ArranqueVF_M->NonInlinedSFcns.taskTimePtrs[0] = (&rtmGetTPtr(ArranqueVF_M)[0]);
    rtssSetTPtrPtr(sfcnInfo,ArranqueVF_M->NonInlinedSFcns.taskTimePtrs);
    rtssSetTStartPtr(sfcnInfo, &rtmGetTStart(ArranqueVF_M));
    rtssSetTFinalPtr(sfcnInfo, &rtmGetTFinal(ArranqueVF_M));
    rtssSetTimeOfLastOutputPtr(sfcnInfo, &rtmGetTimeOfLastOutput(ArranqueVF_M));
    rtssSetStepSizePtr(sfcnInfo, &ArranqueVF_M->Timing.stepSize);
    rtssSetStopRequestedPtr(sfcnInfo, &rtmGetStopRequested(ArranqueVF_M));
    rtssSetDerivCacheNeedsResetPtr(sfcnInfo, &ArranqueVF_M->derivCacheNeedsReset);
    rtssSetZCCacheNeedsResetPtr(sfcnInfo, &ArranqueVF_M->zCCacheNeedsReset);
    rtssSetContTimeOutputInconsistentWithStateAtMajorStepPtr(sfcnInfo,
      &ArranqueVF_M->CTOutputIncnstWithState);
    rtssSetSampleHitsPtr(sfcnInfo, &ArranqueVF_M->Timing.sampleHits);
    rtssSetPerTaskSampleHitsPtr(sfcnInfo,
      &ArranqueVF_M->Timing.perTaskSampleHits);
    rtssSetSimModePtr(sfcnInfo, &ArranqueVF_M->simMode);
    rtssSetSolverInfoPtr(sfcnInfo, &ArranqueVF_M->solverInfoPtr);
  }

  ArranqueVF_M->Sizes.numSFcns = (2);

  /* register each child */
  {
    (void) std::memset(static_cast<void *>
                       (&ArranqueVF_M->NonInlinedSFcns.childSFunctions[0]), 0,
                       2*sizeof(SimStruct));
    ArranqueVF_M->childSfunctions =
      (&ArranqueVF_M->NonInlinedSFcns.childSFunctionPtrs[0]);
    ArranqueVF_M->childSfunctions[0] =
      (&ArranqueVF_M->NonInlinedSFcns.childSFunctions[0]);
    ArranqueVF_M->childSfunctions[1] =
      (&ArranqueVF_M->NonInlinedSFcns.childSFunctions[1]);

    /* Level2 S-Function Block: ArranqueVF/<Root>/Digital output1 (sg_fpga_do_sf_a2) */
    {
      SimStruct *rts = ArranqueVF_M->childSfunctions[0];

      /* timing info */
      time_T *sfcnPeriod = ArranqueVF_M->NonInlinedSFcns.Sfcn0.sfcnPeriod;
      time_T *sfcnOffset = ArranqueVF_M->NonInlinedSFcns.Sfcn0.sfcnOffset;
      int_T *sfcnTsMap = ArranqueVF_M->NonInlinedSFcns.Sfcn0.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts, &ArranqueVF_M->NonInlinedSFcns.blkInfo2[0]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &ArranqueVF_M->NonInlinedSFcns.inputOutputPortInfo2[0]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, ArranqueVF_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts, &ArranqueVF_M->NonInlinedSFcns.methods2[0]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts, &ArranqueVF_M->NonInlinedSFcns.methods3[0]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts, &ArranqueVF_M->NonInlinedSFcns.methods4[0]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts, &ArranqueVF_M->NonInlinedSFcns.statesInfo2[0]);
        ssSetPeriodicStatesInfo(rts,
          &ArranqueVF_M->NonInlinedSFcns.periodicStatesInfo[0]);
      }

      /* inputs */
      {
        _ssSetNumInputPorts(rts, 3);
        ssSetPortInfoForInputs(rts,
          &ArranqueVF_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
        ssSetPortInfoForInputs(rts,
          &ArranqueVF_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
        _ssSetPortInfo2ForInputUnits(rts,
          &ArranqueVF_M->NonInlinedSFcns.Sfcn0.inputPortUnits[0]);
        ssSetInputPortUnit(rts, 0, 0);
        ssSetInputPortUnit(rts, 1, 0);
        ssSetInputPortUnit(rts, 2, 0);
        _ssSetPortInfo2ForInputCoSimAttribute(rts,
          &ArranqueVF_M->NonInlinedSFcns.Sfcn0.inputPortCoSimAttribute[0]);
        ssSetInputPortIsContinuousQuantity(rts, 0, 0);
        ssSetInputPortIsContinuousQuantity(rts, 1, 0);
        ssSetInputPortIsContinuousQuantity(rts, 2, 0);

        /* port 0 */
        {
          ssSetInputPortRequiredContiguous(rts, 0, 1);
          ssSetInputPortSignal(rts, 0, (const_cast<real_T*>(&ArranqueVF_RGND)));
          _ssSetInputPortNumDimensions(rts, 0, 1);
          ssSetInputPortWidthAsInt(rts, 0, 1);
        }

        /* port 1 */
        {
          ssSetInputPortRequiredContiguous(rts, 1, 1);
          ssSetInputPortSignal(rts, 1, (const_cast<real_T*>(&ArranqueVF_RGND)));
          _ssSetInputPortNumDimensions(rts, 1, 1);
          ssSetInputPortWidthAsInt(rts, 1, 1);
        }

        /* port 2 */
        {
          ssSetInputPortRequiredContiguous(rts, 2, 1);
          ssSetInputPortSignal(rts, 2, &ArranqueVF_B.Constant);
          _ssSetInputPortNumDimensions(rts, 2, 1);
          ssSetInputPortWidthAsInt(rts, 2, 1);
        }
      }

      /* path info */
      ssSetModelName(rts, "Digital output1");
      ssSetPath(rts, "ArranqueVF/Digital output1");
      ssSetRTModel(rts,ArranqueVF_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &ArranqueVF_M->NonInlinedSFcns.Sfcn0.params;
        ssSetSFcnParamsCount(rts, 6);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)ArranqueVF_cal->Digitaloutput1_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)ArranqueVF_cal->Digitaloutput1_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)ArranqueVF_cal->Digitaloutput1_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)ArranqueVF_cal->Digitaloutput1_P4_Size);
        ssSetSFcnParam(rts, 4, (mxArray*)ArranqueVF_cal->Digitaloutput1_P5_Size);
        ssSetSFcnParam(rts, 5, (mxArray*)ArranqueVF_cal->Digitaloutput1_P6_Size);
      }

      /* work vectors */
      ssSetIWork(rts, (int_T *) &ArranqueVF_DW.Digitaloutput1_IWORK);
      ssSetPWork(rts, (void **) &ArranqueVF_DW.Digitaloutput1_PWORK[0]);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &ArranqueVF_M->NonInlinedSFcns.Sfcn0.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &ArranqueVF_M->NonInlinedSFcns.Sfcn0.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 2);

        /* IWORK */
        ssSetDWorkWidthAsInt(rts, 0, 1);
        ssSetDWorkDataType(rts, 0,SS_INTEGER);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0, &ArranqueVF_DW.Digitaloutput1_IWORK);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 1, 2);
        ssSetDWorkDataType(rts, 1,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 1, 0);
        ssSetDWork(rts, 1, &ArranqueVF_DW.Digitaloutput1_PWORK[0]);
      }

      /* registration */
      sg_fpga_do_sf_a2(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, 0.0001);
      ssSetOffsetTime(rts, 0, 0.0);
      sfcnTsMap[0] = 0;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      _ssSetInputPortConnected(rts, 0, 0);
      _ssSetInputPortConnected(rts, 1, 0);
      _ssSetInputPortConnected(rts, 2, 1);

      /* Update the BufferDstPort flags for each input port */
      ssSetInputPortBufferDstPort(rts, 0, -1);
      ssSetInputPortBufferDstPort(rts, 1, -1);
      ssSetInputPortBufferDstPort(rts, 2, -1);
    }

    /* Level2 S-Function Block: ArranqueVF/<Root>/Digital output (sg_fpga_do_sf_a2) */
    {
      SimStruct *rts = ArranqueVF_M->childSfunctions[1];

      /* timing info */
      time_T *sfcnPeriod = ArranqueVF_M->NonInlinedSFcns.Sfcn1.sfcnPeriod;
      time_T *sfcnOffset = ArranqueVF_M->NonInlinedSFcns.Sfcn1.sfcnOffset;
      int_T *sfcnTsMap = ArranqueVF_M->NonInlinedSFcns.Sfcn1.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts, &ArranqueVF_M->NonInlinedSFcns.blkInfo2[1]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &ArranqueVF_M->NonInlinedSFcns.inputOutputPortInfo2[1]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, ArranqueVF_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts, &ArranqueVF_M->NonInlinedSFcns.methods2[1]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts, &ArranqueVF_M->NonInlinedSFcns.methods3[1]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts, &ArranqueVF_M->NonInlinedSFcns.methods4[1]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts, &ArranqueVF_M->NonInlinedSFcns.statesInfo2[1]);
        ssSetPeriodicStatesInfo(rts,
          &ArranqueVF_M->NonInlinedSFcns.periodicStatesInfo[1]);
      }

      /* inputs */
      {
        _ssSetNumInputPorts(rts, 3);
        ssSetPortInfoForInputs(rts,
          &ArranqueVF_M->NonInlinedSFcns.Sfcn1.inputPortInfo[0]);
        ssSetPortInfoForInputs(rts,
          &ArranqueVF_M->NonInlinedSFcns.Sfcn1.inputPortInfo[0]);
        _ssSetPortInfo2ForInputUnits(rts,
          &ArranqueVF_M->NonInlinedSFcns.Sfcn1.inputPortUnits[0]);
        ssSetInputPortUnit(rts, 0, 0);
        ssSetInputPortUnit(rts, 1, 0);
        ssSetInputPortUnit(rts, 2, 0);
        _ssSetPortInfo2ForInputCoSimAttribute(rts,
          &ArranqueVF_M->NonInlinedSFcns.Sfcn1.inputPortCoSimAttribute[0]);
        ssSetInputPortIsContinuousQuantity(rts, 0, 0);
        ssSetInputPortIsContinuousQuantity(rts, 1, 0);
        ssSetInputPortIsContinuousQuantity(rts, 2, 0);

        /* port 0 */
        {
          ssSetInputPortRequiredContiguous(rts, 0, 1);
          ssSetInputPortSignal(rts, 0, (const_cast<real_T*>(&ArranqueVF_RGND)));
          _ssSetInputPortNumDimensions(rts, 0, 1);
          ssSetInputPortWidthAsInt(rts, 0, 1);
        }

        /* port 1 */
        {
          ssSetInputPortRequiredContiguous(rts, 1, 1);
          ssSetInputPortSignal(rts, 1, (const_cast<real_T*>(&ArranqueVF_RGND)));
          _ssSetInputPortNumDimensions(rts, 1, 1);
          ssSetInputPortWidthAsInt(rts, 1, 1);
        }

        /* port 2 */
        {
          ssSetInputPortRequiredContiguous(rts, 2, 1);
          ssSetInputPortSignal(rts, 2, (const_cast<real_T*>(&ArranqueVF_RGND)));
          _ssSetInputPortNumDimensions(rts, 2, 1);
          ssSetInputPortWidthAsInt(rts, 2, 1);
        }
      }

      /* path info */
      ssSetModelName(rts, "Digital output");
      ssSetPath(rts, "ArranqueVF/Digital output");
      ssSetRTModel(rts,ArranqueVF_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &ArranqueVF_M->NonInlinedSFcns.Sfcn1.params;
        ssSetSFcnParamsCount(rts, 6);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)ArranqueVF_cal->Digitaloutput_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)ArranqueVF_cal->Digitaloutput_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)ArranqueVF_cal->Digitaloutput_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)ArranqueVF_cal->Digitaloutput_P4_Size);
        ssSetSFcnParam(rts, 4, (mxArray*)ArranqueVF_cal->Digitaloutput_P5_Size);
        ssSetSFcnParam(rts, 5, (mxArray*)ArranqueVF_cal->Digitaloutput_P6_Size);
      }

      /* work vectors */
      ssSetIWork(rts, (int_T *) &ArranqueVF_DW.Digitaloutput_IWORK);
      ssSetPWork(rts, (void **) &ArranqueVF_DW.Digitaloutput_PWORK[0]);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &ArranqueVF_M->NonInlinedSFcns.Sfcn1.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &ArranqueVF_M->NonInlinedSFcns.Sfcn1.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 2);

        /* IWORK */
        ssSetDWorkWidthAsInt(rts, 0, 1);
        ssSetDWorkDataType(rts, 0,SS_INTEGER);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0, &ArranqueVF_DW.Digitaloutput_IWORK);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 1, 2);
        ssSetDWorkDataType(rts, 1,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 1, 0);
        ssSetDWork(rts, 1, &ArranqueVF_DW.Digitaloutput_PWORK[0]);
      }

      /* registration */
      sg_fpga_do_sf_a2(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, 0.0001);
      ssSetOffsetTime(rts, 0, 0.0);
      sfcnTsMap[0] = 0;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      _ssSetInputPortConnected(rts, 0, 0);
      _ssSetInputPortConnected(rts, 1, 0);
      _ssSetInputPortConnected(rts, 2, 0);

      /* Update the BufferDstPort flags for each input port */
      ssSetInputPortBufferDstPort(rts, 0, -1);
      ssSetInputPortBufferDstPort(rts, 1, -1);
      ssSetInputPortBufferDstPort(rts, 2, -1);
    }
  }

  /* Start for Constant: '<Root>/Constant' */
  ArranqueVF_B.Constant = ArranqueVF_cal->Constant_Value;

  /* Start for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output1' */
  /* Level2 S-Function Block: '<Root>/Digital output1' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = ArranqueVF_M->childSfunctions[0];
    sfcnStart(rts);
    if (ssGetErrorStatus(rts) != (NULL))
      return;
  }

  /* Start for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
  /* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = ArranqueVF_M->childSfunctions[1];
    sfcnStart(rts);
    if (ssGetErrorStatus(rts) != (NULL))
      return;
  }
}

/* Model terminate function */
void ArranqueVF_terminate(void)
{
  /* Terminate for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output1' */
  /* Level2 S-Function Block: '<Root>/Digital output1' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = ArranqueVF_M->childSfunctions[0];
    sfcnTerminate(rts);
  }

  /* Terminate for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
  /* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
  {
    SimStruct *rts = ArranqueVF_M->childSfunctions[1];
    sfcnTerminate(rts);
  }

  /* user code (Terminate function Trailer) */
  {
    freeFPGAModuleSgLib((uint32_t)1);
  }
}