/*
 * Alinear_encoder.cpp
 *
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * Code generation for model "Alinear_encoder".
 *
 * Model version              : 1.3
 * Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
 * C++ source code generated on : Fri Aug 22 11:49:38 2025
 *
 * Target selection: speedgoat.tlc
 * Note: GRT includes extra infrastructure and instrumentation for prototyping
 * Embedded hardware selection: Intel->x86-64 (Linux 64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#include "Alinear_encoder.h"
#include "Alinear_encoder_cal.h"
#include "rtwtypes.h"
#include "rte_Alinear_encoder_parameters.h"
#include "Alinear_encoder_private.h"
#include "zero_crossing_types.h"
#include <cstring>

extern "C"
{

#include "rt_nonfinite.h"

}

/* Block signals (default storage) */
B_Alinear_encoder_T Alinear_encoder_B;

/* Block states (default storage) */
DW_Alinear_encoder_T Alinear_encoder_DW;

/* Previous zero-crossings (trigger) states */
PrevZCX_Alinear_encoder_T Alinear_encoder_PrevZCX;

/* Real-time model */
RT_MODEL_Alinear_encoder_T Alinear_encoder_M_ = RT_MODEL_Alinear_encoder_T();
RT_MODEL_Alinear_encoder_T *const Alinear_encoder_M = &Alinear_encoder_M_;

/* Model step function */
void Alinear_encoder_step(void)
{
  boolean_T zcEvent;
  ZCEventType zcEvent_0;

  /* Reset subsysRan breadcrumbs */
  srClearBC(Alinear_encoder_DW.TriggeredSubsystem_SubsysRanBC);

  /* Reset subsysRan breadcrumbs */
  srClearBC(Alinear_encoder_DW.NEGATIVEEdge_SubsysRanBC);

  /* Reset subsysRan breadcrumbs */
  srClearBC(Alinear_encoder_DW.POSITIVEEdge_SubsysRanBC);

  /* Reset subsysRan breadcrumbs */
  srClearBC(Alinear_encoder_DW.SampleandHold_SubsysRanBC);

  /* Constant: '<Root>/Constant1' */
  Alinear_encoder_B.Constant1 = Alinear_encoder_cal->Constant1_Value;

  /* S-Function (sg_fpga_di_sf_a2): '<Root>/Encoder1' */

  /* Level2 S-Function Block: '<Root>/Encoder1' (sg_fpga_di_sf_a2) */
  {
    SimStruct *rts = Alinear_encoder_M->childSfunctions[0];
    sfcnOutputs(rts,0);
  }

  /* DataTypeConversion: '<S4>/Data Type Conversion2' */
  Alinear_encoder_B.DataTypeConversion2 = (Alinear_encoder_B.Encoder1_o1 != 0.0);

  /* Memory: '<S4>/Memory' */
  Alinear_encoder_B.Memory = Alinear_encoder_DW.Memory_PreviousInput;

  /* MultiPortSwitch: '<S4>/Multiport Switch' incorporates:
   *  Constant: '<S4>/Constant1'
   */
  switch (static_cast<int32_T>(Alinear_encoder_cal->EdgeDetector_model)) {
   case 1:
    /* MultiPortSwitch: '<S4>/Multiport Switch' incorporates:
     *  Constant: '<S4>/pos. edge'
     */
    Alinear_encoder_B.MultiportSwitch[0] = Alinear_encoder_cal->posedge_Value[0];
    Alinear_encoder_B.MultiportSwitch[1] = Alinear_encoder_cal->posedge_Value[1];
    break;

   case 2:
    /* MultiPortSwitch: '<S4>/Multiport Switch' incorporates:
     *  Constant: '<S4>/neg. edge'
     */
    Alinear_encoder_B.MultiportSwitch[0] = Alinear_encoder_cal->negedge_Value[0];
    Alinear_encoder_B.MultiportSwitch[1] = Alinear_encoder_cal->negedge_Value[1];
    break;

   default:
    /* MultiPortSwitch: '<S4>/Multiport Switch' incorporates:
     *  Constant: '<S4>/either edge'
     */
    Alinear_encoder_B.MultiportSwitch[0] = Alinear_encoder_cal->
      eitheredge_Value[0];
    Alinear_encoder_B.MultiportSwitch[1] = Alinear_encoder_cal->
      eitheredge_Value[1];
    break;
  }

  /* End of MultiPortSwitch: '<S4>/Multiport Switch' */

  /* Outputs for Enabled SubSystem: '<S4>/POSITIVE Edge' incorporates:
   *  EnablePort: '<S7>/Enable'
   */
  Alinear_encoder_DW.POSITIVEEdge_MODE = (Alinear_encoder_B.MultiportSwitch[0] >
    0.0);
  if (Alinear_encoder_DW.POSITIVEEdge_MODE) {
    /* RelationalOperator: '<S7>/Relational Operator1' */
    Alinear_encoder_B.RelationalOperator1 = (static_cast<int32_T>
      (Alinear_encoder_B.Memory) < static_cast<int32_T>
      (Alinear_encoder_B.DataTypeConversion2));
    srUpdateBC(Alinear_encoder_DW.POSITIVEEdge_SubsysRanBC);
  }

  /* End of Outputs for SubSystem: '<S4>/POSITIVE Edge' */

  /* Outputs for Enabled SubSystem: '<S4>/NEGATIVE Edge' incorporates:
   *  EnablePort: '<S6>/Enable'
   */
  Alinear_encoder_DW.NEGATIVEEdge_MODE = (Alinear_encoder_B.MultiportSwitch[1] >
    0.0);
  if (Alinear_encoder_DW.NEGATIVEEdge_MODE) {
    /* RelationalOperator: '<S6>/Relational Operator1' */
    Alinear_encoder_B.RelationalOperator1_d = (static_cast<int32_T>
      (Alinear_encoder_B.Memory) > static_cast<int32_T>
      (Alinear_encoder_B.DataTypeConversion2));
    srUpdateBC(Alinear_encoder_DW.NEGATIVEEdge_SubsysRanBC);
  }

  /* End of Outputs for SubSystem: '<S4>/NEGATIVE Edge' */

  /* Logic: '<S4>/Logical Operator1' */
  Alinear_encoder_B.LogicalOperator1 = (Alinear_encoder_B.RelationalOperator1 ||
    Alinear_encoder_B.RelationalOperator1_d);

  /* DataTypeConversion: '<S1>/Data Type Conversion' */
  Alinear_encoder_B.DataTypeConversion = Alinear_encoder_B.LogicalOperator1;

  /* Delay: '<S1>/Delay1' */
  Alinear_encoder_B.Delay1 = Alinear_encoder_DW.Delay1_DSTATE;

  /* Switch: '<S1>/Switch2' */
  if (Alinear_encoder_B.Encoder1_o3 > Alinear_encoder_cal->Switch2_Threshold) {
    /* Switch: '<S1>/Switch2' incorporates:
     *  Constant: '<S1>/Constant'
     */
    Alinear_encoder_B.Switch2 = Alinear_encoder_cal->Constant_Value;
  } else {
    /* Logic: '<S1>/Logical Operator' */
    Alinear_encoder_B.LogicalOperator = (Alinear_encoder_B.LogicalOperator1 &&
      (Alinear_encoder_B.Encoder1_o2 != 0.0));

    /* Switch: '<S1>/Switch' */
    if (Alinear_encoder_B.LogicalOperator) {
      /* Switch: '<S1>/Switch' */
      Alinear_encoder_B.Switch = Alinear_encoder_B.DataTypeConversion;
    } else {
      /* Gain: '<S1>/Gain1' */
      Alinear_encoder_B.Gain1 = Alinear_encoder_cal->Gain1_Gain *
        Alinear_encoder_B.DataTypeConversion;

      /* Switch: '<S1>/Switch' */
      Alinear_encoder_B.Switch = Alinear_encoder_B.Gain1;
    }

    /* End of Switch: '<S1>/Switch' */

    /* Sum: '<S1>/Sum' */
    Alinear_encoder_B.Sum_l = Alinear_encoder_B.Switch +
      Alinear_encoder_B.Delay1;

    /* Switch: '<S1>/Switch2' */
    Alinear_encoder_B.Switch2 = Alinear_encoder_B.Sum_l;
  }

  /* End of Switch: '<S1>/Switch2' */

  /* Gain: '<S1>/CTE Encoder' */
  Alinear_encoder_B.CTEEncoder = *get_cte_encoder() * Alinear_encoder_B.Switch2;

  /* Sum: '<S1>/Sum2' incorporates:
   *  Constant: '<S1>/Constant1'
   */
  Alinear_encoder_B.Sum2 = Alinear_encoder_B.CTEEncoder + *get_desfase_z_d();

  /* Delay: '<S1>/Delay2' */
  Alinear_encoder_B.Delay2 = Alinear_encoder_DW.Delay2_DSTATE[0];

  /* Clock: '<S5>/Clock' */
  Alinear_encoder_B.Clock = Alinear_encoder_M->Timing.t[0];

  /* Outputs for Triggered SubSystem: '<S5>/Triggered Subsystem' incorporates:
   *  TriggerPort: '<S8>/Trigger'
   */
  zcEvent = (Alinear_encoder_B.LogicalOperator1 &&
             (Alinear_encoder_PrevZCX.TriggeredSubsystem_Trig_ZCE != POS_ZCSIG));
  if (zcEvent) {
    /* SignalConversion generated from: '<S8>/In1' */
    Alinear_encoder_B.In1 = Alinear_encoder_B.Clock;
    Alinear_encoder_DW.TriggeredSubsystem_SubsysRanBC = 4;
  }

  Alinear_encoder_PrevZCX.TriggeredSubsystem_Trig_ZCE =
    Alinear_encoder_B.LogicalOperator1;

  /* End of Outputs for SubSystem: '<S5>/Triggered Subsystem' */

  /* Sum: '<S5>/Sum' incorporates:
   *  Constant: '<S5>/Constant'
   */
  Alinear_encoder_B.Sum = Alinear_encoder_B.In1 +
    Alinear_encoder_cal->Constant_Value_p;

  /* RelationalOperator: '<S5>/Relational Operator' */
  Alinear_encoder_B.RelationalOperator = (Alinear_encoder_B.Sum >
    Alinear_encoder_B.Clock);

  /* Sum: '<S1>/Sum1' */
  Alinear_encoder_B.Sum1 = Alinear_encoder_B.CTEEncoder -
    Alinear_encoder_B.Delay2;

  /* Gain: '<S1>/Gain Velocidad' */
  Alinear_encoder_B.GainVelocidad = *get_gain_velocidad() *
    Alinear_encoder_B.Sum1;

  /* Outputs for Triggered SubSystem: '<Root>/Sample and Hold' incorporates:
   *  TriggerPort: '<S2>/Trigger'
   */
  zcEvent_0 = rt_ZCFcn(RISING_ZERO_CROSSING,
                       &Alinear_encoder_PrevZCX.SampleandHold_Trig_ZCE,
                       (Alinear_encoder_B.Encoder1_o3));
  if (zcEvent_0 != NO_ZCEVENT) {
    /* SignalConversion generated from: '<S2>/In' */
    Alinear_encoder_B.In = Alinear_encoder_B.Sum2;
    Alinear_encoder_DW.SampleandHold_SubsysRanBC = 4;
  }

  /* End of Outputs for SubSystem: '<Root>/Sample and Hold' */
  /* user code (Output function Trailer) */
  {
  }

  /* Update for Memory: '<S4>/Memory' */
  Alinear_encoder_DW.Memory_PreviousInput =
    Alinear_encoder_B.DataTypeConversion2;

  /* Update for Delay: '<S1>/Delay1' */
  Alinear_encoder_DW.Delay1_DSTATE = Alinear_encoder_B.Switch2;

  /* Update for Delay: '<S1>/Delay2' */
  for (int32_T idxDelay = 0; idxDelay < 199; idxDelay++) {
    Alinear_encoder_DW.Delay2_DSTATE[idxDelay] =
      Alinear_encoder_DW.Delay2_DSTATE[idxDelay + 1];
  }

  Alinear_encoder_DW.Delay2_DSTATE[199] = Alinear_encoder_B.CTEEncoder;

  /* End of Update for Delay: '<S1>/Delay2' */

  /* Update absolute time for base rate */
  /* The "clockTick0" counts the number of times the code of this task has
   * been executed. The absolute time is the multiplication of "clockTick0"
   * and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
   * overflow during the application lifespan selected.
   * Timer of this task consists of two 32 bit unsigned integers.
   * The two integers represent the low bits Timing.clockTick0 and the high bits
   * Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
   */
  if (!(++Alinear_encoder_M->Timing.clockTick0)) {
    ++Alinear_encoder_M->Timing.clockTickH0;
  }

  Alinear_encoder_M->Timing.t[0] = Alinear_encoder_M->Timing.clockTick0 *
    Alinear_encoder_M->Timing.stepSize0 + Alinear_encoder_M->Timing.clockTickH0 *
    Alinear_encoder_M->Timing.stepSize0 * 4294967296.0;

  {
    /* Update absolute timer for sample time: [4.0E-5s, 0.0s] */
    /* The "clockTick1" counts the number of times the code of this task has
     * been executed. The absolute time is the multiplication of "clockTick1"
     * and "Timing.stepSize1". Size of "clockTick1" ensures timer will not
     * overflow during the application lifespan selected.
     * Timer of this task consists of two 32 bit unsigned integers.
     * The two integers represent the low bits Timing.clockTick1 and the high bits
     * Timing.clockTickH1. When the low bit overflows to 0, the high bits increment.
     */
    if (!(++Alinear_encoder_M->Timing.clockTick1)) {
      ++Alinear_encoder_M->Timing.clockTickH1;
    }

    Alinear_encoder_M->Timing.t[1] = Alinear_encoder_M->Timing.clockTick1 *
      Alinear_encoder_M->Timing.stepSize1 +
      Alinear_encoder_M->Timing.clockTickH1 *
      Alinear_encoder_M->Timing.stepSize1 * 4294967296.0;
  }
}

/* Model initialize function */
void Alinear_encoder_initialize(void)
{
  /* Registration code */

  /* initialize non-finites */
  rt_InitInfAndNaN(sizeof(real_T));

  {
    /* Setup solver object */
    rtsiSetSimTimeStepPtr(&Alinear_encoder_M->solverInfo,
                          &Alinear_encoder_M->Timing.simTimeStep);
    rtsiSetTPtr(&Alinear_encoder_M->solverInfo, &rtmGetTPtr(Alinear_encoder_M));
    rtsiSetStepSizePtr(&Alinear_encoder_M->solverInfo,
                       &Alinear_encoder_M->Timing.stepSize0);
    rtsiSetErrorStatusPtr(&Alinear_encoder_M->solverInfo, (&rtmGetErrorStatus
      (Alinear_encoder_M)));
    rtsiSetRTModelPtr(&Alinear_encoder_M->solverInfo, Alinear_encoder_M);
  }

  rtsiSetSimTimeStep(&Alinear_encoder_M->solverInfo, MAJOR_TIME_STEP);
  rtsiSetIsMinorTimeStepWithModeChange(&Alinear_encoder_M->solverInfo, false);
  rtsiSetIsContModeFrozen(&Alinear_encoder_M->solverInfo, false);
  rtsiSetSolverName(&Alinear_encoder_M->solverInfo,"FixedStepDiscrete");
  Alinear_encoder_M->solverInfoPtr = (&Alinear_encoder_M->solverInfo);

  /* Initialize timing info */
  {
    int_T *mdlTsMap = Alinear_encoder_M->Timing.sampleTimeTaskIDArray;
    mdlTsMap[0] = 0;
    mdlTsMap[1] = 1;
    Alinear_encoder_M->Timing.sampleTimeTaskIDPtr = (&mdlTsMap[0]);
    Alinear_encoder_M->Timing.sampleTimes =
      (&Alinear_encoder_M->Timing.sampleTimesArray[0]);
    Alinear_encoder_M->Timing.offsetTimes =
      (&Alinear_encoder_M->Timing.offsetTimesArray[0]);

    /* task periods */
    Alinear_encoder_M->Timing.sampleTimes[0] = (0.0);
    Alinear_encoder_M->Timing.sampleTimes[1] = (4.0E-5);

    /* task offsets */
    Alinear_encoder_M->Timing.offsetTimes[0] = (0.0);
    Alinear_encoder_M->Timing.offsetTimes[1] = (0.0);
  }

  rtmSetTPtr(Alinear_encoder_M, &Alinear_encoder_M->Timing.tArray[0]);

  {
    int_T *mdlSampleHits = Alinear_encoder_M->Timing.sampleHitArray;
    mdlSampleHits[0] = 1;
    mdlSampleHits[1] = 1;
    Alinear_encoder_M->Timing.sampleHits = (&mdlSampleHits[0]);
  }

  rtmSetTFinal(Alinear_encoder_M, -1);
  Alinear_encoder_M->Timing.stepSize0 = 4.0E-5;
  Alinear_encoder_M->Timing.stepSize1 = 4.0E-5;
  Alinear_encoder_M->solverInfoPtr = (&Alinear_encoder_M->solverInfo);
  Alinear_encoder_M->Timing.stepSize = (4.0E-5);
  rtsiSetFixedStepSize(&Alinear_encoder_M->solverInfo, 4.0E-5);
  rtsiSetSolverMode(&Alinear_encoder_M->solverInfo, SOLVER_MODE_SINGLETASKING);

  /* block I/O */
  (void) std::memset((static_cast<void *>(&Alinear_encoder_B)), 0,
                     sizeof(B_Alinear_encoder_T));

  /* states (dwork) */
  (void) std::memset(static_cast<void *>(&Alinear_encoder_DW), 0,
                     sizeof(DW_Alinear_encoder_T));

  /* child S-Function registration */
  {
    RTWSfcnInfo *sfcnInfo = &Alinear_encoder_M->NonInlinedSFcns.sfcnInfo;
    Alinear_encoder_M->sfcnInfo = (sfcnInfo);
    rtssSetErrorStatusPtr(sfcnInfo, (&rtmGetErrorStatus(Alinear_encoder_M)));
    Alinear_encoder_M->Sizes.numSampTimes = (2);
    rtssSetNumRootSampTimesPtr(sfcnInfo, &Alinear_encoder_M->Sizes.numSampTimes);
    Alinear_encoder_M->NonInlinedSFcns.taskTimePtrs[0] = (&rtmGetTPtr
      (Alinear_encoder_M)[0]);
    Alinear_encoder_M->NonInlinedSFcns.taskTimePtrs[1] = (&rtmGetTPtr
      (Alinear_encoder_M)[1]);
    rtssSetTPtrPtr(sfcnInfo,Alinear_encoder_M->NonInlinedSFcns.taskTimePtrs);
    rtssSetTStartPtr(sfcnInfo, &rtmGetTStart(Alinear_encoder_M));
    rtssSetTFinalPtr(sfcnInfo, &rtmGetTFinal(Alinear_encoder_M));
    rtssSetTimeOfLastOutputPtr(sfcnInfo, &rtmGetTimeOfLastOutput
      (Alinear_encoder_M));
    rtssSetStepSizePtr(sfcnInfo, &Alinear_encoder_M->Timing.stepSize);
    rtssSetStopRequestedPtr(sfcnInfo, &rtmGetStopRequested(Alinear_encoder_M));
    rtssSetDerivCacheNeedsResetPtr(sfcnInfo,
      &Alinear_encoder_M->derivCacheNeedsReset);
    rtssSetZCCacheNeedsResetPtr(sfcnInfo, &Alinear_encoder_M->zCCacheNeedsReset);
    rtssSetContTimeOutputInconsistentWithStateAtMajorStepPtr(sfcnInfo,
      &Alinear_encoder_M->CTOutputIncnstWithState);
    rtssSetSampleHitsPtr(sfcnInfo, &Alinear_encoder_M->Timing.sampleHits);
    rtssSetPerTaskSampleHitsPtr(sfcnInfo,
      &Alinear_encoder_M->Timing.perTaskSampleHits);
    rtssSetSimModePtr(sfcnInfo, &Alinear_encoder_M->simMode);
    rtssSetSolverInfoPtr(sfcnInfo, &Alinear_encoder_M->solverInfoPtr);
  }

  Alinear_encoder_M->Sizes.numSFcns = (1);

  /* register each child */
  {
    (void) std::memset(static_cast<void *>
                       (&Alinear_encoder_M->NonInlinedSFcns.childSFunctions[0]),
                       0,
                       1*sizeof(SimStruct));
    Alinear_encoder_M->childSfunctions =
      (&Alinear_encoder_M->NonInlinedSFcns.childSFunctionPtrs[0]);
    Alinear_encoder_M->childSfunctions[0] =
      (&Alinear_encoder_M->NonInlinedSFcns.childSFunctions[0]);

    /* Level2 S-Function Block: Alinear_encoder/<Root>/Encoder1 (sg_fpga_di_sf_a2) */
    {
      SimStruct *rts = Alinear_encoder_M->childSfunctions[0];

      /* timing info */
      time_T *sfcnPeriod = Alinear_encoder_M->NonInlinedSFcns.Sfcn0.sfcnPeriod;
      time_T *sfcnOffset = Alinear_encoder_M->NonInlinedSFcns.Sfcn0.sfcnOffset;
      int_T *sfcnTsMap = Alinear_encoder_M->NonInlinedSFcns.Sfcn0.sfcnTsMap;
      (void) std::memset(static_cast<void*>(sfcnPeriod), 0,
                         sizeof(time_T)*1);
      (void) std::memset(static_cast<void*>(sfcnOffset), 0,
                         sizeof(time_T)*1);
      ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
      ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
      ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);

      {
        ssSetBlkInfo2Ptr(rts, &Alinear_encoder_M->NonInlinedSFcns.blkInfo2[0]);
      }

      _ssSetBlkInfo2PortInfo2Ptr(rts,
        &Alinear_encoder_M->NonInlinedSFcns.inputOutputPortInfo2[0]);

      /* Set up the mdlInfo pointer */
      ssSetRTWSfcnInfo(rts, Alinear_encoder_M->sfcnInfo);

      /* Allocate memory of model methods 2 */
      {
        ssSetModelMethods2(rts, &Alinear_encoder_M->NonInlinedSFcns.methods2[0]);
      }

      /* Allocate memory of model methods 3 */
      {
        ssSetModelMethods3(rts, &Alinear_encoder_M->NonInlinedSFcns.methods3[0]);
      }

      /* Allocate memory of model methods 4 */
      {
        ssSetModelMethods4(rts, &Alinear_encoder_M->NonInlinedSFcns.methods4[0]);
      }

      /* Allocate memory for states auxilliary information */
      {
        ssSetStatesInfo2(rts, &Alinear_encoder_M->NonInlinedSFcns.statesInfo2[0]);
        ssSetPeriodicStatesInfo(rts,
          &Alinear_encoder_M->NonInlinedSFcns.periodicStatesInfo[0]);
      }

      /* outputs */
      {
        ssSetPortInfoForOutputs(rts,
          &Alinear_encoder_M->NonInlinedSFcns.Sfcn0.outputPortInfo[0]);
        ssSetPortInfoForOutputs(rts,
          &Alinear_encoder_M->NonInlinedSFcns.Sfcn0.outputPortInfo[0]);
        _ssSetNumOutputPorts(rts, 3);
        _ssSetPortInfo2ForOutputUnits(rts,
          &Alinear_encoder_M->NonInlinedSFcns.Sfcn0.outputPortUnits[0]);
        ssSetOutputPortUnit(rts, 0, 0);
        ssSetOutputPortUnit(rts, 1, 0);
        ssSetOutputPortUnit(rts, 2, 0);
        _ssSetPortInfo2ForOutputCoSimAttribute(rts,
          &Alinear_encoder_M->NonInlinedSFcns.Sfcn0.outputPortCoSimAttribute[0]);
        ssSetOutputPortIsContinuousQuantity(rts, 0, 0);
        ssSetOutputPortIsContinuousQuantity(rts, 1, 0);
        ssSetOutputPortIsContinuousQuantity(rts, 2, 0);

        /* port 0 */
        {
          _ssSetOutputPortNumDimensions(rts, 0, 1);
          ssSetOutputPortWidthAsInt(rts, 0, 1);
          ssSetOutputPortSignal(rts, 0, ((real_T *)
            &Alinear_encoder_B.Encoder1_o1));
        }

        /* port 1 */
        {
          _ssSetOutputPortNumDimensions(rts, 1, 1);
          ssSetOutputPortWidthAsInt(rts, 1, 1);
          ssSetOutputPortSignal(rts, 1, ((real_T *)
            &Alinear_encoder_B.Encoder1_o2));
        }

        /* port 2 */
        {
          _ssSetOutputPortNumDimensions(rts, 2, 1);
          ssSetOutputPortWidthAsInt(rts, 2, 1);
          ssSetOutputPortSignal(rts, 2, ((real_T *)
            &Alinear_encoder_B.Encoder1_o3));
        }
      }

      /* path info */
      ssSetModelName(rts, "Encoder1");
      ssSetPath(rts, "Alinear_encoder/Encoder1");
      ssSetRTModel(rts,Alinear_encoder_M);
      ssSetParentSS(rts, (NULL));
      ssSetRootSS(rts, rts);
      ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);

      /* parameters */
      {
        mxArray **sfcnParams = (mxArray **)
          &Alinear_encoder_M->NonInlinedSFcns.Sfcn0.params;
        ssSetSFcnParamsCount(rts, 4);
        ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
        ssSetSFcnParam(rts, 0, (mxArray*)Alinear_encoder_cal->Encoder1_P1_Size);
        ssSetSFcnParam(rts, 1, (mxArray*)Alinear_encoder_cal->Encoder1_P2_Size);
        ssSetSFcnParam(rts, 2, (mxArray*)Alinear_encoder_cal->Encoder1_P3_Size);
        ssSetSFcnParam(rts, 3, (mxArray*)Alinear_encoder_cal->Encoder1_P4_Size);
      }

      /* work vectors */
      ssSetPWork(rts, (void **) &Alinear_encoder_DW.Encoder1_PWORK[0]);

      {
        struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
          &Alinear_encoder_M->NonInlinedSFcns.Sfcn0.dWork;
        struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
          &Alinear_encoder_M->NonInlinedSFcns.Sfcn0.dWorkAux;
        ssSetSFcnDWork(rts, dWorkRecord);
        ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
        ssSetNumDWorkAsInt(rts, 1);

        /* PWORK */
        ssSetDWorkWidthAsInt(rts, 0, 2);
        ssSetDWorkDataType(rts, 0,SS_POINTER);
        ssSetDWorkComplexSignal(rts, 0, 0);
        ssSetDWork(rts, 0, &Alinear_encoder_DW.Encoder1_PWORK[0]);
      }

      /* registration */
      sg_fpga_di_sf_a2(rts);
      sfcnInitializeSizes(rts);
      sfcnInitializeSampleTimes(rts);

      /* adjust sample time */
      ssSetSampleTime(rts, 0, 4.0E-5);
      ssSetOffsetTime(rts, 0, 0.0);
      sfcnTsMap[0] = 1;

      /* set compiled values of dynamic vector attributes */
      ssSetNumNonsampledZCsAsInt(rts, 0);

      /* Update connectivity flags for each port */
      _ssSetOutputPortConnected(rts, 0, 1);
      _ssSetOutputPortConnected(rts, 1, 1);
      _ssSetOutputPortConnected(rts, 2, 1);
      _ssSetOutputPortBeingMerged(rts, 0, 0);
      _ssSetOutputPortBeingMerged(rts, 1, 0);
      _ssSetOutputPortBeingMerged(rts, 2, 0);

      /* Update the BufferDstPort flags for each input port */
    }
  }

  /* Start for S-Function (sg_fpga_di_sf_a2): '<Root>/Encoder1' */
  /* Level2 S-Function Block: '<Root>/Encoder1' (sg_fpga_di_sf_a2) */
  {
    SimStruct *rts = Alinear_encoder_M->childSfunctions[0];
    sfcnStart(rts);
    if (ssGetErrorStatus(rts) != (NULL))
      return;
  }

  Alinear_encoder_PrevZCX.TriggeredSubsystem_Trig_ZCE = POS_ZCSIG;
  Alinear_encoder_PrevZCX.SampleandHold_Trig_ZCE = UNINITIALIZED_ZCSIG;

  {
    int32_T i;

    /* InitializeConditions for Memory: '<S4>/Memory' */
    Alinear_encoder_DW.Memory_PreviousInput =
      Alinear_encoder_cal->EdgeDetector_ic;

    /* InitializeConditions for Delay: '<S1>/Delay1' */
    Alinear_encoder_DW.Delay1_DSTATE =
      Alinear_encoder_cal->Delay1_InitialCondition;

    /* InitializeConditions for Delay: '<S1>/Delay2' */
    for (i = 0; i < 200; i++) {
      Alinear_encoder_DW.Delay2_DSTATE[i] =
        Alinear_encoder_cal->Delay2_InitialCondition;
    }

    /* End of InitializeConditions for Delay: '<S1>/Delay2' */

    /* SystemInitialize for Enabled SubSystem: '<S4>/POSITIVE Edge' */
    /* SystemInitialize for RelationalOperator: '<S7>/Relational Operator1' incorporates:
     *  Outport: '<S7>/OUT'
     */
    Alinear_encoder_B.RelationalOperator1 = Alinear_encoder_cal->OUT_Y0_c;

    /* End of SystemInitialize for SubSystem: '<S4>/POSITIVE Edge' */

    /* SystemInitialize for Enabled SubSystem: '<S4>/NEGATIVE Edge' */
    /* SystemInitialize for RelationalOperator: '<S6>/Relational Operator1' incorporates:
     *  Outport: '<S6>/OUT'
     */
    Alinear_encoder_B.RelationalOperator1_d = Alinear_encoder_cal->OUT_Y0;

    /* End of SystemInitialize for SubSystem: '<S4>/NEGATIVE Edge' */

    /* SystemInitialize for Triggered SubSystem: '<S5>/Triggered Subsystem' */
    /* SystemInitialize for SignalConversion generated from: '<S8>/In1' incorporates:
     *  Outport: '<S8>/Out1'
     */
    Alinear_encoder_B.In1 = Alinear_encoder_cal->Out1_Y0;

    /* End of SystemInitialize for SubSystem: '<S5>/Triggered Subsystem' */

    /* SystemInitialize for Triggered SubSystem: '<Root>/Sample and Hold' */
    /* SystemInitialize for SignalConversion generated from: '<S2>/In' incorporates:
     *  Outport: '<S2>/ '
     */
    Alinear_encoder_B.In = Alinear_encoder_cal->_Y0;

    /* End of SystemInitialize for SubSystem: '<Root>/Sample and Hold' */
  }
}

/* Model terminate function */
void Alinear_encoder_terminate(void)
{
  /* Terminate for S-Function (sg_fpga_di_sf_a2): '<Root>/Encoder1' */
  /* Level2 S-Function Block: '<Root>/Encoder1' (sg_fpga_di_sf_a2) */
  {
    SimStruct *rts = Alinear_encoder_M->childSfunctions[0];
    sfcnTerminate(rts);
  }

  /* user code (Terminate function Trailer) */
  {
    freeFPGAModuleSgLib((uint32_t)1);
  }
}