/*
 * Alinear_encoder.h
 *
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * Code generation for model "Alinear_encoder".
 *
 * Model version              : 1.3
 * Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
 * C++ source code generated on : Fri Aug 22 11:49:38 2025
 *
 * Target selection: speedgoat.tlc
 * Note: GRT includes extra infrastructure and instrumentation for prototyping
 * Embedded hardware selection: Intel->x86-64 (Linux 64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#ifndef Alinear_encoder_h_
#define Alinear_encoder_h_
#include "rtwtypes.h"
#include "simstruc.h"
#include "fixedpoint.h"
#include "sg_fpga_io30x_setup_util.h"
#include "sg_fpga_io31x_io32x_setup_util.h"
#include "sg_fpga_io33x_setup_util.h"
#include "sg_fpga_io36x_setup_util.h"
#include "sg_fpga_io39x_setup_util.h"
#include "sg_fpga_io3xx_scatter_gather_dma.h"
#include "sg_fpga_nigora_setup_util.h"
#include "sg_common.h"
#include "sg_printf.h"
#include "Alinear_encoder_types.h"
#include <stddef.h>
#include "rt_zcfcn.h"
#include <cstring>
#include "Alinear_encoder_cal.h"

extern "C"
{

#include "rt_nonfinite.h"

}

#include "zero_crossing_types.h"

/* Macros for accessing real-time model data structure */
#ifndef rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag
#define rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm) ((rtm)->CTOutputIncnstWithState)
#endif

#ifndef rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag
#define rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm, val) ((rtm)->CTOutputIncnstWithState = (val))
#endif

#ifndef rtmGetDerivCacheNeedsReset
#define rtmGetDerivCacheNeedsReset(rtm) ((rtm)->derivCacheNeedsReset)
#endif

#ifndef rtmSetDerivCacheNeedsReset
#define rtmSetDerivCacheNeedsReset(rtm, val) ((rtm)->derivCacheNeedsReset = (val))
#endif

#ifndef rtmGetFinalTime
#define rtmGetFinalTime(rtm)           ((rtm)->Timing.tFinal)
#endif

#ifndef rtmGetSampleHitArray
#define rtmGetSampleHitArray(rtm)      ((rtm)->Timing.sampleHitArray)
#endif

#ifndef rtmGetStepSize
#define rtmGetStepSize(rtm)            ((rtm)->Timing.stepSize)
#endif

#ifndef rtmGetZCCacheNeedsReset
#define rtmGetZCCacheNeedsReset(rtm)   ((rtm)->zCCacheNeedsReset)
#endif

#ifndef rtmSetZCCacheNeedsReset
#define rtmSetZCCacheNeedsReset(rtm, val) ((rtm)->zCCacheNeedsReset = (val))
#endif

#ifndef rtmGet_TimeOfLastOutput
#define rtmGet_TimeOfLastOutput(rtm)   ((rtm)->Timing.timeOfLastOutput)
#endif

#ifndef rtmGetErrorStatus
#define rtmGetErrorStatus(rtm)         ((rtm)->errorStatus)
#endif

#ifndef rtmSetErrorStatus
#define rtmSetErrorStatus(rtm, val)    ((rtm)->errorStatus = (val))
#endif

#ifndef rtmGetStopRequested
#define rtmGetStopRequested(rtm)       ((rtm)->Timing.stopRequestedFlag)
#endif

#ifndef rtmSetStopRequested
#define rtmSetStopRequested(rtm, val)  ((rtm)->Timing.stopRequestedFlag = (val))
#endif

#ifndef rtmGetStopRequestedPtr
#define rtmGetStopRequestedPtr(rtm)    (&((rtm)->Timing.stopRequestedFlag))
#endif

#ifndef rtmGetT
#define rtmGetT(rtm)                   (rtmGetTPtr((rtm))[0])
#endif

#ifndef rtmGetTFinal
#define rtmGetTFinal(rtm)              ((rtm)->Timing.tFinal)
#endif

#ifndef rtmGetTPtr
#define rtmGetTPtr(rtm)                ((rtm)->Timing.t)
#endif

#ifndef rtmGetTStart
#define rtmGetTStart(rtm)              ((rtm)->Timing.tStart)
#endif

#ifndef rtmGetTimeOfLastOutput
#define rtmGetTimeOfLastOutput(rtm)    ((rtm)->Timing.timeOfLastOutput)
#endif

/* Block signals (default storage) */
struct B_Alinear_encoder_T {
  real_T Constant1;                    /* '<Root>/Constant1' */
  real_T Encoder1_o1;                  /* '<Root>/Encoder1' */
  real_T Encoder1_o2;                  /* '<Root>/Encoder1' */
  real_T Encoder1_o3;                  /* '<Root>/Encoder1' */
  real_T MultiportSwitch[2];           /* '<S4>/Multiport Switch' */
  real_T DataTypeConversion;           /* '<S1>/Data Type Conversion' */
  real_T Delay1;                       /* '<S1>/Delay1' */
  real_T Switch2;                      /* '<S1>/Switch2' */
  real_T CTEEncoder;                   /* '<S1>/CTE Encoder' */
  real_T Sum2;                         /* '<S1>/Sum2' */
  real_T Delay2;                       /* '<S1>/Delay2' */
  real_T Clock;                        /* '<S5>/Clock' */
  real_T Sum;                          /* '<S5>/Sum' */
  real_T Sum1;                         /* '<S1>/Sum1' */
  real_T GainVelocidad;                /* '<S1>/Gain Velocidad' */
  real_T In;                           /* '<S2>/In' */
  real_T Switch;                       /* '<S1>/Switch' */
  real_T Sum_l;                        /* '<S1>/Sum' */
  real_T Gain1;                        /* '<S1>/Gain1' */
  real_T In1;                          /* '<S8>/In1' */
  boolean_T DataTypeConversion2;       /* '<S4>/Data Type Conversion2' */
  boolean_T Memory;                    /* '<S4>/Memory' */
  boolean_T LogicalOperator1;          /* '<S4>/Logical Operator1' */
  boolean_T RelationalOperator;        /* '<S5>/Relational Operator' */
  boolean_T LogicalOperator;           /* '<S1>/Logical Operator' */
  boolean_T RelationalOperator1;       /* '<S7>/Relational Operator1' */
  boolean_T RelationalOperator1_d;     /* '<S6>/Relational Operator1' */
};

/* Block states (default storage) for system '<Root>' */
struct DW_Alinear_encoder_T {
  real_T Delay1_DSTATE;                /* '<S1>/Delay1' */
  real_T Delay2_DSTATE[200];           /* '<S1>/Delay2' */
  void *Encoder1_PWORK[2];             /* '<Root>/Encoder1' */
  struct {
    void *LoggedData[2];
  } Scope_PWORK;                       /* '<Root>/Scope' */

  struct {
    void *USERIO_P_IND;
    void *PROG_SPACE_P_IND;
    void *CONFIG_REGISTER_P_IND;
    void *CONDITIONING_MODULE_IO3xx_2x_P_IND;
    void *DEVICENAME_P_IND;
    void *DMA_CONTROLLER_P_IND;
  } Setup_PWORK;                       /* '<Root>/Setup' */

  struct {
    int_T MODULEARCHITECTURE_I_IND;
  } Setup_IWORK;                       /* '<Root>/Setup' */

  int8_T SampleandHold_SubsysRanBC;    /* '<Root>/Sample and Hold' */
  int8_T POSITIVEEdge_SubsysRanBC;     /* '<S4>/POSITIVE Edge' */
  int8_T NEGATIVEEdge_SubsysRanBC;     /* '<S4>/NEGATIVE Edge' */
  int8_T TriggeredSubsystem_SubsysRanBC;/* '<S5>/Triggered Subsystem' */
  boolean_T Memory_PreviousInput;      /* '<S4>/Memory' */
  boolean_T POSITIVEEdge_MODE;         /* '<S4>/POSITIVE Edge' */
  boolean_T NEGATIVEEdge_MODE;         /* '<S4>/NEGATIVE Edge' */
};

/* Zero-crossing (trigger) state */
struct PrevZCX_Alinear_encoder_T {
  ZCSigState SampleandHold_Trig_ZCE;   /* '<Root>/Sample and Hold' */
  ZCSigState TriggeredSubsystem_Trig_ZCE;/* '<S5>/Triggered Subsystem' */
};

/* Real-time Model Data Structure */
struct tag_RTM_Alinear_encoder_T {
  struct SimStruct_tag * *childSfunctions;
  const char_T *errorStatus;
  SS_SimMode simMode;
  RTWSolverInfo solverInfo;
  RTWSolverInfo *solverInfoPtr;
  void *sfcnInfo;

  /*
   * NonInlinedSFcns:
   * The following substructure contains information regarding
   * non-inlined s-functions used in the model.
   */
  struct {
    RTWSfcnInfo sfcnInfo;
    time_T *taskTimePtrs[2];
    SimStruct childSFunctions[1];
    SimStruct *childSFunctionPtrs[1];
    struct _ssBlkInfo2 blkInfo2[1];
    struct _ssSFcnModelMethods2 methods2[1];
    struct _ssSFcnModelMethods3 methods3[1];
    struct _ssSFcnModelMethods4 methods4[1];
    struct _ssStatesInfo2 statesInfo2[1];
    ssPeriodicStatesInfo periodicStatesInfo[1];
    struct _ssPortInfo2 inputOutputPortInfo2[1];
    struct {
      time_T sfcnPeriod[1];
      time_T sfcnOffset[1];
      int_T sfcnTsMap[1];
      struct _ssPortOutputs outputPortInfo[3];
      struct _ssOutPortUnit outputPortUnits[3];
      struct _ssOutPortCoSimAttribute outputPortCoSimAttribute[3];
      uint_T attribs[4];
      mxArray *params[4];
      struct _ssDWorkRecord dWork[1];
      struct _ssDWorkAuxRecord dWorkAux[1];
    } Sfcn0;
  } NonInlinedSFcns;

  boolean_T zCCacheNeedsReset;
  boolean_T derivCacheNeedsReset;
  boolean_T CTOutputIncnstWithState;

  /*
   * Sizes:
   * The following substructure contains sizes information
   * for many of the model attributes such as inputs, outputs,
   * dwork, sample times, etc.
   */
  struct {
    uint32_T options;
    int_T numContStates;
    int_T numU;
    int_T numY;
    int_T numSampTimes;
    int_T numBlocks;
    int_T numBlockIO;
    int_T numBlockPrms;
    int_T numDwork;
    int_T numSFcnPrms;
    int_T numSFcns;
    int_T numIports;
    int_T numOports;
    int_T numNonSampZCs;
    int_T sysDirFeedThru;
    int_T rtwGenSfcn;
  } Sizes;

  /*
   * Timing:
   * The following substructure contains information regarding
   * the timing information for the model.
   */
  struct {
    time_T stepSize;
    uint32_T clockTick0;
    uint32_T clockTickH0;
    time_T stepSize0;
    uint32_T clockTick1;
    uint32_T clockTickH1;
    time_T stepSize1;
    time_T tStart;
    time_T tFinal;
    time_T timeOfLastOutput;
    SimTimeStep simTimeStep;
    boolean_T stopRequestedFlag;
    time_T *sampleTimes;
    time_T *offsetTimes;
    int_T *sampleTimeTaskIDPtr;
    int_T *sampleHits;
    int_T *perTaskSampleHits;
    time_T *t;
    time_T sampleTimesArray[2];
    time_T offsetTimesArray[2];
    int_T sampleTimeTaskIDArray[2];
    int_T sampleHitArray[2];
    int_T perTaskSampleHitsArray[4];
    time_T tArray[2];
  } Timing;
};

/* Block signals (default storage) */
#ifdef __cplusplus

extern "C"
{

#endif

  extern struct B_Alinear_encoder_T Alinear_encoder_B;

#ifdef __cplusplus

}

#endif

/* Block states (default storage) */
extern struct DW_Alinear_encoder_T Alinear_encoder_DW;

/* Zero-crossing (trigger) state */
extern PrevZCX_Alinear_encoder_T Alinear_encoder_PrevZCX;

#ifdef __cplusplus

extern "C"
{

#endif

  /* Model entry point functions */
  extern void Alinear_encoder_initialize(void);
  extern void Alinear_encoder_step(void);
  extern void Alinear_encoder_terminate(void);

#ifdef __cplusplus

}

#endif

/* Real-time Model object */
#ifdef __cplusplus

extern "C"
{

#endif

  extern RT_MODEL_Alinear_encoder_T *const Alinear_encoder_M;

#ifdef __cplusplus

}

#endif

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'Alinear_encoder'
 * '<S1>'   : 'Alinear_encoder/Decodificador'
 * '<S2>'   : 'Alinear_encoder/Sample and Hold'
 * '<S3>'   : 'Alinear_encoder/Decodificador/Edge Detector'
 * '<S4>'   : 'Alinear_encoder/Decodificador/Edge Detector/Model'
 * '<S5>'   : 'Alinear_encoder/Decodificador/Edge Detector/Model/Internal dirac generator'
 * '<S6>'   : 'Alinear_encoder/Decodificador/Edge Detector/Model/NEGATIVE Edge'
 * '<S7>'   : 'Alinear_encoder/Decodificador/Edge Detector/Model/POSITIVE Edge'
 * '<S8>'   : 'Alinear_encoder/Decodificador/Edge Detector/Model/Internal dirac generator/Triggered Subsystem'
 */
#endif                                 /* Alinear_encoder_h_ */