/* * control_Velocidad.h * * Academic License - for use in teaching, academic research, and meeting * course requirements at degree granting institutions only. Not for * government, commercial, or other organizational use. * * Code generation for model "control_Velocidad". * * Model version : 1.10 * Simulink Coder version : 24.2 (R2024b) 21-Jun-2024 * C++ source code generated on : Mon Jun 9 17:59:10 2025 * * Target selection: speedgoat.tlc * Note: GRT includes extra infrastructure and instrumentation for prototyping * Embedded hardware selection: Intel->x86-64 (Linux 64) * Code generation objectives: Unspecified * Validation result: Not run */ #ifndef control_Velocidad_h_ #define control_Velocidad_h_ #include "rtwtypes.h" #include "simstruc.h" #include "fixedpoint.h" #include "sg_fpga_io30x_setup_util.h" #include "sg_fpga_io31x_io32x_setup_util.h" #include "sg_fpga_io33x_setup_util.h" #include "sg_fpga_io36x_setup_util.h" #include "sg_fpga_io39x_setup_util.h" #include "sg_fpga_io3xx_scatter_gather_dma.h" #include "sg_fpga_nigora_setup_util.h" #include "sg_common.h" #include "sg_printf.h" #include "control_Velocidad_types.h" #include extern "C" { #include "rtGetNaN.h" } #include #include "control_Velocidad_cal.h" extern "C" { #include "rt_nonfinite.h" } #include "zero_crossing_types.h" /* Macros for accessing real-time model data structure */ #ifndef rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag #define rtmGetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm) ((rtm)->CTOutputIncnstWithState) #endif #ifndef rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag #define rtmSetContTimeOutputInconsistentWithStateAtMajorStepFlag(rtm, val) ((rtm)->CTOutputIncnstWithState = (val)) #endif #ifndef rtmGetDerivCacheNeedsReset #define rtmGetDerivCacheNeedsReset(rtm) ((rtm)->derivCacheNeedsReset) #endif #ifndef rtmSetDerivCacheNeedsReset #define rtmSetDerivCacheNeedsReset(rtm, val) ((rtm)->derivCacheNeedsReset = (val)) #endif #ifndef rtmGetFinalTime #define rtmGetFinalTime(rtm) ((rtm)->Timing.tFinal) #endif #ifndef rtmGetSampleHitArray #define rtmGetSampleHitArray(rtm) ((rtm)->Timing.sampleHitArray) #endif #ifndef rtmGetStepSize #define rtmGetStepSize(rtm) ((rtm)->Timing.stepSize) #endif #ifndef rtmGetZCCacheNeedsReset #define rtmGetZCCacheNeedsReset(rtm) ((rtm)->zCCacheNeedsReset) #endif #ifndef rtmSetZCCacheNeedsReset #define rtmSetZCCacheNeedsReset(rtm, val) ((rtm)->zCCacheNeedsReset = (val)) #endif #ifndef rtmGet_TimeOfLastOutput #define rtmGet_TimeOfLastOutput(rtm) ((rtm)->Timing.timeOfLastOutput) #endif #ifndef rtmCounterLimit #define rtmCounterLimit(rtm, idx) ((rtm)->Timing.TaskCounters.cLimit[(idx)]) #endif #ifndef rtmGetErrorStatus #define rtmGetErrorStatus(rtm) ((rtm)->errorStatus) #endif #ifndef rtmSetErrorStatus #define rtmSetErrorStatus(rtm, val) ((rtm)->errorStatus = (val)) #endif #ifndef rtmStepTask #define rtmStepTask(rtm, idx) ((rtm)->Timing.TaskCounters.TID[(idx)] == 0) #endif #ifndef rtmGetStopRequested #define rtmGetStopRequested(rtm) ((rtm)->Timing.stopRequestedFlag) #endif #ifndef rtmSetStopRequested #define rtmSetStopRequested(rtm, val) ((rtm)->Timing.stopRequestedFlag = (val)) #endif #ifndef rtmGetStopRequestedPtr #define rtmGetStopRequestedPtr(rtm) (&((rtm)->Timing.stopRequestedFlag)) #endif #ifndef rtmGetT #define rtmGetT(rtm) (rtmGetTPtr((rtm))[0]) #endif #ifndef rtmGetTFinal #define rtmGetTFinal(rtm) ((rtm)->Timing.tFinal) #endif #ifndef rtmGetTPtr #define rtmGetTPtr(rtm) ((rtm)->Timing.t) #endif #ifndef rtmGetTStart #define rtmGetTStart(rtm) ((rtm)->Timing.tStart) #endif #ifndef rtmTaskCounter #define rtmTaskCounter(rtm, idx) ((rtm)->Timing.TaskCounters.TID[(idx)]) #endif #ifndef rtmGetTimeOfLastOutput #define rtmGetTimeOfLastOutput(rtm) ((rtm)->Timing.timeOfLastOutput) #endif /* Block signals (default storage) */ struct B_control_Velocidad_T { uint64_T CTEEncoder; /* '/CTE Encoder' */ real_T CTE_amplitud; /* '/CTE_amplitud' */ real_T DiscreteTimeIntegrator; /* '/Discrete-Time Integrator' */ real_T TrigonometricFunction; /* '/Trigonometric Function' */ real_T Sum; /* '/Sum' */ real_T TrigonometricFunction1; /* '/Trigonometric Function1' */ real_T Sum1; /* '/Sum1' */ real_T TrigonometricFunction2; /* '/Trigonometric Function2' */ real_T Product[3]; /* '/Product' */ real_T Saturation[3]; /* '/Saturation' */ real_T DigitalClock; /* '/Digital Clock' */ real_T Add1; /* '/Add1' */ real_T MathFunction; /* '/Math Function' */ real_T uib1; /* '/1\ib1' */ real_T uDLookupTable; /* '/1-D Lookup Table' */ real_T Add3; /* '/Add3' */ real_T Add3_b; /* '/Add3' */ real_T Gain1; /* '/Gain1' */ real_T MUL1; /* '/MUL1' */ real_T Add4; /* '/Add4' */ real_T DataTypeConversion[6]; /* '/Data Type Conversion' */ real_T Gain; /* '/Gain' */ real_T Delay1; /* '/Delay1' */ real_T Digitalinput_o1; /* '/Digital input' */ real_T Digitalinput_o2; /* '/Digital input' */ real_T MultiportSwitch[2]; /* '/Multiport Switch' */ real_T Clock; /* '/Clock' */ real_T Uk1; /* '/UD' */ real_T Diff; /* '/Diff' */ real_T Delay; /* '/Delay' */ real_T Switch; /* '/Switch' */ real_T Product_o; /* '/Product' */ real_T Add; /* '/Add' */ real_T Clock_e; /* '/Clock' */ real_T Sum_g; /* '/Sum' */ real_T IO397AnalogInput_o1; /* '/IO397 Analog Input' */ real_T IO397AnalogInput_o2; /* '/IO397 Analog Input' */ real_T IO397AnalogInput_o3; /* '/IO397 Analog Input' */ real_T Gain_n; /* '/Gain' */ real_T Gain1_j; /* '/Gain1' */ real_T Gain2; /* '/Gain2' */ real_T Switch1; /* '/Switch1' */ real_T In; /* '/In' */ real_T In1; /* '/In1' */ boolean_T RelationalOperator2[3]; /* '/Relational Operator2' */ boolean_T LogicalOperator4[3]; /* '/Logical Operator4' */ boolean_T CastToBoolean; /* '/Cast To Boolean' */ boolean_T DataTypeConversion2; /* '/Data Type Conversion2' */ boolean_T Memory; /* '/Memory' */ boolean_T LogicalOperator1; /* '/Logical Operator1' */ boolean_T CastToBoolean1; /* '/Cast To Boolean1' */ boolean_T RelationalOperator; /* '/Relational Operator' */ boolean_T LogicalOperator; /* '/Logical Operator' */ boolean_T RelationalOperator1; /* '/Relational Operator1' */ boolean_T RelationalOperator1_e; /* '/Relational Operator1' */ }; /* Block states (default storage) for system '' */ struct DW_control_Velocidad_T { real_T DiscreteTimeIntegrator_DSTATE;/* '/Discrete-Time Integrator' */ real_T Delay1_DSTATE; /* '/Delay1' */ real_T UD_DSTATE; /* '/UD' */ real_T Delay_DSTATE; /* '/Delay' */ void *Digitaloutput_PWORK[2]; /* '/Digital output' */ void *Digitalinput_PWORK[2]; /* '/Digital input' */ struct { void *LoggedData[2]; } Scope2_PWORK; /* '/Scope2' */ struct { void *USERIO_P_IND; void *PROG_SPACE_P_IND; void *CONFIG_REGISTER_P_IND; void *CONDITIONING_MODULE_IO3xx_2x_P_IND; void *DEVICENAME_P_IND; void *DMA_CONTROLLER_P_IND; } Setup_PWORK; /* '/Setup' */ void *IO397AnalogInput_PWORK[3]; /* '/IO397 Analog Input' */ struct { void *LoggedData[3]; } Scope1_PWORK; /* '/Scope1' */ uint32_T m_bpIndex; /* '/1-D Lookup Table' */ int_T Digitaloutput_IWORK; /* '/Digital output' */ struct { int_T MODULEARCHITECTURE_I_IND; } Setup_IWORK; /* '/Setup' */ int8_T SampleandHold1_SubsysRanBC; /* '/Sample and Hold1' */ int8_T POSITIVEEdge_SubsysRanBC; /* '/POSITIVE Edge' */ int8_T NEGATIVEEdge_SubsysRanBC; /* '/NEGATIVE Edge' */ int8_T TriggeredSubsystem_SubsysRanBC;/* '/Triggered Subsystem' */ boolean_T Memory_PreviousInput; /* '/Memory' */ boolean_T POSITIVEEdge_MODE; /* '/POSITIVE Edge' */ boolean_T NEGATIVEEdge_MODE; /* '/NEGATIVE Edge' */ }; /* Zero-crossing (trigger) state */ struct PrevZCX_control_Velocidad_T { ZCSigState SampleandHold1_Trig_ZCE; /* '/Sample and Hold1' */ ZCSigState TriggeredSubsystem_Trig_ZCE;/* '/Triggered Subsystem' */ }; /* Real-time Model Data Structure */ struct tag_RTM_control_Velocidad_T { struct SimStruct_tag * *childSfunctions; const char_T *errorStatus; SS_SimMode simMode; RTWSolverInfo solverInfo; RTWSolverInfo *solverInfoPtr; void *sfcnInfo; /* * NonInlinedSFcns: * The following substructure contains information regarding * non-inlined s-functions used in the model. */ struct { RTWSfcnInfo sfcnInfo; time_T *taskTimePtrs[3]; SimStruct childSFunctions[3]; SimStruct *childSFunctionPtrs[3]; struct _ssBlkInfo2 blkInfo2[3]; struct _ssSFcnModelMethods2 methods2[3]; struct _ssSFcnModelMethods3 methods3[3]; struct _ssSFcnModelMethods4 methods4[3]; struct _ssStatesInfo2 statesInfo2[3]; ssPeriodicStatesInfo periodicStatesInfo[3]; struct _ssPortInfo2 inputOutputPortInfo2[3]; struct { time_T sfcnPeriod[1]; time_T sfcnOffset[1]; int_T sfcnTsMap[1]; struct _ssPortInputs inputPortInfo[6]; struct _ssInPortUnit inputPortUnits[6]; struct _ssInPortCoSimAttribute inputPortCoSimAttribute[6]; uint_T attribs[6]; mxArray *params[6]; struct _ssDWorkRecord dWork[2]; struct _ssDWorkAuxRecord dWorkAux[2]; } Sfcn0; struct { time_T sfcnPeriod[1]; time_T sfcnOffset[1]; int_T sfcnTsMap[1]; struct _ssPortOutputs outputPortInfo[2]; struct _ssOutPortUnit outputPortUnits[2]; struct _ssOutPortCoSimAttribute outputPortCoSimAttribute[2]; uint_T attribs[4]; mxArray *params[4]; struct _ssDWorkRecord dWork[1]; struct _ssDWorkAuxRecord dWorkAux[1]; } Sfcn1; struct { time_T sfcnPeriod[1]; time_T sfcnOffset[1]; int_T sfcnTsMap[1]; struct _ssPortOutputs outputPortInfo[3]; struct _ssOutPortUnit outputPortUnits[3]; struct _ssOutPortCoSimAttribute outputPortCoSimAttribute[3]; uint_T attribs[9]; mxArray *params[9]; struct _ssDWorkRecord dWork[1]; struct _ssDWorkAuxRecord dWorkAux[1]; } Sfcn2; } NonInlinedSFcns; boolean_T zCCacheNeedsReset; boolean_T derivCacheNeedsReset; boolean_T CTOutputIncnstWithState; /* * Sizes: * The following substructure contains sizes information * for many of the model attributes such as inputs, outputs, * dwork, sample times, etc. */ struct { uint32_T options; int_T numContStates; int_T numU; int_T numY; int_T numSampTimes; int_T numBlocks; int_T numBlockIO; int_T numBlockPrms; int_T numDwork; int_T numSFcnPrms; int_T numSFcns; int_T numIports; int_T numOports; int_T numNonSampZCs; int_T sysDirFeedThru; int_T rtwGenSfcn; } Sizes; /* * Timing: * The following substructure contains information regarding * the timing information for the model. */ struct { time_T stepSize; uint32_T clockTick0; uint32_T clockTickH0; time_T stepSize0; uint32_T clockTick1; uint32_T clockTickH1; time_T stepSize1; uint32_T clockTick2; uint32_T clockTickH2; time_T stepSize2; struct { uint8_T TID[3]; uint8_T cLimit[3]; } TaskCounters; time_T tStart; time_T tFinal; time_T timeOfLastOutput; SimTimeStep simTimeStep; boolean_T stopRequestedFlag; time_T *sampleTimes; time_T *offsetTimes; int_T *sampleTimeTaskIDPtr; int_T *sampleHits; int_T *perTaskSampleHits; time_T *t; time_T sampleTimesArray[3]; time_T offsetTimesArray[3]; int_T sampleTimeTaskIDArray[3]; int_T sampleHitArray[3]; int_T perTaskSampleHitsArray[9]; time_T tArray[3]; } Timing; }; /* Block signals (default storage) */ #ifdef __cplusplus extern "C" { #endif extern struct B_control_Velocidad_T control_Velocidad_B; #ifdef __cplusplus } #endif /* Block states (default storage) */ extern struct DW_control_Velocidad_T control_Velocidad_DW; /* Zero-crossing (trigger) state */ extern PrevZCX_control_Velocidad_T control_Velocidad_PrevZCX; #ifdef __cplusplus extern "C" { #endif /* Model entry point functions */ extern void control_Velocidad_initialize(void); extern void control_Velocidad_step0(void);/* Sample time: [0.0s, 0.0s] */ extern void control_Velocidad_step2(void);/* Sample time: [0.001s, 0.0s] */ extern void control_Velocidad_terminate(void); #ifdef __cplusplus } #endif /* Real-time Model object */ #ifdef __cplusplus extern "C" { #endif extern RT_MODEL_control_Velocidad_T *const control_Velocidad_M; #ifdef __cplusplus } #endif /*- * The generated code includes comments that allow you to trace directly * back to the appropriate location in the model. The basic format * is /block_name, where system is the system number (uniquely * assigned by Simulink) and block_name is the name of the block. * * Use the MATLAB hilite_system command to trace the generated code back * to the model. For example, * * hilite_system('') - opens system 3 * hilite_system('/Kp') - opens and selects block Kp which resides in S3 * * Here is the system hierarchy for this model * * '' : 'control_Velocidad' * '' : 'control_Velocidad/Generador Trifasica Unitario' * '' : 'control_Velocidad/PWM Generator (2-Level)' * '' : 'control_Velocidad/Subsystem1' * '' : 'control_Velocidad/PWM Generator (2-Level)/Cr_MinMax' * '' : 'control_Velocidad/PWM Generator (2-Level)/Modulator type' * '' : 'control_Velocidad/PWM Generator (2-Level)/Reference signal' * '' : 'control_Velocidad/PWM Generator (2-Level)/Sampling' * '' : 'control_Velocidad/PWM Generator (2-Level)/Modulator type/One Three Phase Bridge' * '' : 'control_Velocidad/PWM Generator (2-Level)/Reference signal/External' * '' : 'control_Velocidad/PWM Generator (2-Level)/Sampling/Unsync Natural' * '' : 'control_Velocidad/PWM Generator (2-Level)/Sampling/Unsync Natural/Unsync_NaturalSampling' * '' : 'control_Velocidad/PWM Generator (2-Level)/Sampling/Unsync Natural/Unsync_NaturalSampling/Triangle Generator' * '' : 'control_Velocidad/PWM Generator (2-Level)/Sampling/Unsync Natural/Unsync_NaturalSampling/Triangle Generator/Model' * '' : 'control_Velocidad/Subsystem1/Difference1' * '' : 'control_Velocidad/Subsystem1/Edge Detector' * '' : 'control_Velocidad/Subsystem1/Sample and Hold1' * '' : 'control_Velocidad/Subsystem1/Edge Detector/Model' * '' : 'control_Velocidad/Subsystem1/Edge Detector/Model/Internal dirac generator' * '' : 'control_Velocidad/Subsystem1/Edge Detector/Model/NEGATIVE Edge' * '' : 'control_Velocidad/Subsystem1/Edge Detector/Model/POSITIVE Edge' * '' : 'control_Velocidad/Subsystem1/Edge Detector/Model/Internal dirac generator/Triggered Subsystem' */ #endif /* control_Velocidad_h_ */