587 lines
20 KiB
C++
587 lines
20 KiB
C++
/*
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* Test_LOGICA_3FPWM.cpp
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*
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* Academic License - for use in teaching, academic research, and meeting
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* course requirements at degree granting institutions only. Not for
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* government, commercial, or other organizational use.
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*
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* Code generation for model "Test_LOGICA_3FPWM".
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*
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* Model version : 1.48
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* Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
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* C++ source code generated on : Wed Jul 23 11:33:04 2025
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*
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* Target selection: speedgoat.tlc
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* Note: GRT includes extra infrastructure and instrumentation for prototyping
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* Embedded hardware selection: Intel->x86-64 (Linux 64)
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* Code generation objectives: Unspecified
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* Validation result: Not run
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*/
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#include "Test_LOGICA_3FPWM.h"
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#include "Test_LOGICA_3FPWM_cal.h"
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#include "Test_LOGICA_3FPWM_private.h"
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#include "rtwtypes.h"
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#include <cstring>
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extern "C"
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{
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#include "rt_nonfinite.h"
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}
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#include <cmath>
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#include <cfloat>
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/* Block signals (default storage) */
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B_Test_LOGICA_3FPWM_T Test_LOGICA_3FPWM_B;
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/* Block states (default storage) */
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DW_Test_LOGICA_3FPWM_T Test_LOGICA_3FPWM_DW;
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/* Real-time model */
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RT_MODEL_Test_LOGICA_3FPWM_T Test_LOGICA_3FPWM_M_ = RT_MODEL_Test_LOGICA_3FPWM_T
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();
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RT_MODEL_Test_LOGICA_3FPWM_T *const Test_LOGICA_3FPWM_M = &Test_LOGICA_3FPWM_M_;
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real_T look1_pbinlxpw(real_T u0, const real_T bp0[], const real_T table[],
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uint32_T prevIndex[], uint32_T maxIndex)
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{
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real_T frac;
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real_T yL_0d0;
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uint32_T bpIdx;
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/* Column-major Lookup 1-D
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Search method: 'binary'
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Use previous index: 'on'
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Interpolation method: 'Linear point-slope'
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Extrapolation method: 'Linear'
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Use last breakpoint for index at or above upper limit: 'off'
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Remove protection against out-of-range input in generated code: 'off'
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*/
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/* Prelookup - Index and Fraction
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Index Search method: 'binary'
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Extrapolation method: 'Linear'
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Use previous index: 'on'
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Use last breakpoint for index at or above upper limit: 'off'
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Remove protection against out-of-range input in generated code: 'off'
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*/
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if (u0 <= bp0[0U]) {
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bpIdx = 0U;
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frac = (u0 - bp0[0U]) / (bp0[1U] - bp0[0U]);
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} else if (u0 < bp0[maxIndex]) {
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uint32_T found;
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uint32_T iLeft;
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uint32_T iRght;
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/* Binary Search using Previous Index */
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bpIdx = prevIndex[0U];
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iLeft = 0U;
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iRght = maxIndex;
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found = 0U;
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while (found == 0U) {
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if (u0 < bp0[bpIdx]) {
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iRght = bpIdx - 1U;
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bpIdx = ((bpIdx + iLeft) - 1U) >> 1U;
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} else if (u0 < bp0[bpIdx + 1U]) {
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found = 1U;
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} else {
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iLeft = bpIdx + 1U;
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bpIdx = ((bpIdx + iRght) + 1U) >> 1U;
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}
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}
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frac = (u0 - bp0[bpIdx]) / (bp0[bpIdx + 1U] - bp0[bpIdx]);
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} else {
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bpIdx = maxIndex - 1U;
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frac = (u0 - bp0[maxIndex - 1U]) / (bp0[maxIndex] - bp0[maxIndex - 1U]);
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}
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prevIndex[0U] = bpIdx;
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/* Column-major Interpolation 1-D
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Interpolation method: 'Linear point-slope'
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Use last breakpoint for index at or above upper limit: 'off'
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Overflow mode: 'portable wrapping'
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*/
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yL_0d0 = table[bpIdx];
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return (table[bpIdx + 1U] - yL_0d0) * frac + yL_0d0;
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}
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real_T rt_remd_snf(real_T u0, real_T u1)
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{
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real_T y;
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if (rtIsNaN(u0) || rtIsNaN(u1) || rtIsInf(u0)) {
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y = (rtNaN);
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} else if (rtIsInf(u1)) {
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y = u0;
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} else {
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if (u1 < 0.0) {
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y = std::ceil(u1);
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} else {
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y = std::floor(u1);
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}
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if ((u1 != 0.0) && (u1 != y)) {
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real_T q;
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q = std::abs(u0 / u1);
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if (!(std::abs(q - std::floor(q + 0.5)) > DBL_EPSILON * q)) {
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y = 0.0 * u0;
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} else {
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y = std::fmod(u0, u1);
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}
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} else {
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y = std::fmod(u0, u1);
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}
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}
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return y;
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}
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/* Model step function */
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void Test_LOGICA_3FPWM_step(void)
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{
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/* DigitalClock: '<S11>/Digital Clock' */
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Test_LOGICA_3FPWM_B.DigitalClock = Test_LOGICA_3FPWM_M->Timing.t[0];
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/* Sum: '<S11>/Add1' incorporates:
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* Constant: '<S11>/Constant3'
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*/
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Test_LOGICA_3FPWM_B.Add1 = Test_LOGICA_3FPWM_B.DigitalClock +
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Test_LOGICA_3FPWM_cal->Constant3_Value;
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/* Math: '<S11>/Math Function' incorporates:
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* Constant: '<S11>/Constant1'
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*/
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Test_LOGICA_3FPWM_B.MathFunction = rt_remd_snf(Test_LOGICA_3FPWM_B.Add1,
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Test_LOGICA_3FPWM_cal->Constant1_Value);
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/* Gain: '<S11>/1\ib1' */
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Test_LOGICA_3FPWM_B.uib1 = Test_LOGICA_3FPWM_cal->uib1_Gain *
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Test_LOGICA_3FPWM_B.MathFunction;
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/* Lookup_n-D: '<S11>/1-D Lookup Table' incorporates:
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* Gain: '<S11>/1\ib1'
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*/
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Test_LOGICA_3FPWM_B.uDLookupTable = look1_pbinlxpw(Test_LOGICA_3FPWM_B.uib1,
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Test_LOGICA_3FPWM_cal->uDLookupTable_bp01Data,
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Test_LOGICA_3FPWM_cal->uDLookupTable_tableData,
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&Test_LOGICA_3FPWM_DW.m_bpIndex, 2U);
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/* Sum: '<S11>/Add3' incorporates:
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* Constant: '<S11>/Constant2'
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*/
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Test_LOGICA_3FPWM_B.Add3 = Test_LOGICA_3FPWM_B.uDLookupTable -
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Test_LOGICA_3FPWM_cal->Constant2_Value;
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/* Sum: '<S2>/Add3' incorporates:
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* Constant: '<S1>/Constant10'
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*/
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Test_LOGICA_3FPWM_B.Add3_j = Test_LOGICA_3FPWM_cal->PWMGenerator2Level_MinMax
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[1] - Test_LOGICA_3FPWM_cal->PWMGenerator2Level_MinMax[0];
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/* Gain: '<S2>/Gain1' */
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Test_LOGICA_3FPWM_B.Gain1 = Test_LOGICA_3FPWM_cal->Gain1_Gain *
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Test_LOGICA_3FPWM_B.Add3_j;
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/* Product: '<S2>/MUL1' */
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Test_LOGICA_3FPWM_B.MUL1 = Test_LOGICA_3FPWM_B.Add3 *
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Test_LOGICA_3FPWM_B.Gain1;
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/* Sum: '<S2>/Add4' incorporates:
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* Constant: '<S1>/Constant10'
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*/
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Test_LOGICA_3FPWM_B.Add4 = (Test_LOGICA_3FPWM_cal->PWMGenerator2Level_MinMax[0]
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+ Test_LOGICA_3FPWM_B.MUL1) + Test_LOGICA_3FPWM_B.Gain1;
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/* RelationalOperator: '<S6>/Relational Operator2' incorporates:
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* Constant: '<Root>/Va'
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* Constant: '<Root>/Vb'
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* Constant: '<Root>/Vc'
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*/
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Test_LOGICA_3FPWM_B.RelationalOperator2[0] = (Test_LOGICA_3FPWM_cal->Va_Value >=
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Test_LOGICA_3FPWM_B.Add4);
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Test_LOGICA_3FPWM_B.RelationalOperator2[1] = (Test_LOGICA_3FPWM_cal->Vb_Value >=
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Test_LOGICA_3FPWM_B.Add4);
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Test_LOGICA_3FPWM_B.RelationalOperator2[2] = (Test_LOGICA_3FPWM_cal->Vc_Value >=
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Test_LOGICA_3FPWM_B.Add4);
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/* Logic: '<S1>/Logical Operator4' */
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Test_LOGICA_3FPWM_B.LogicalOperator4[0] =
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!Test_LOGICA_3FPWM_B.RelationalOperator2[0];
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Test_LOGICA_3FPWM_B.LogicalOperator4[1] =
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!Test_LOGICA_3FPWM_B.RelationalOperator2[1];
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Test_LOGICA_3FPWM_B.LogicalOperator4[2] =
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!Test_LOGICA_3FPWM_B.RelationalOperator2[2];
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/* DataTypeConversion: '<S1>/Data Type Conversion' */
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Test_LOGICA_3FPWM_B.DataTypeConversion[0] =
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Test_LOGICA_3FPWM_B.RelationalOperator2[0];
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Test_LOGICA_3FPWM_B.DataTypeConversion[1] =
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Test_LOGICA_3FPWM_B.LogicalOperator4[0];
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Test_LOGICA_3FPWM_B.DataTypeConversion[2] =
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Test_LOGICA_3FPWM_B.RelationalOperator2[1];
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Test_LOGICA_3FPWM_B.DataTypeConversion[3] =
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Test_LOGICA_3FPWM_B.LogicalOperator4[1];
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Test_LOGICA_3FPWM_B.DataTypeConversion[4] =
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Test_LOGICA_3FPWM_B.RelationalOperator2[2];
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Test_LOGICA_3FPWM_B.DataTypeConversion[5] =
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Test_LOGICA_3FPWM_B.LogicalOperator4[2];
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/* S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
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/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
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{
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SimStruct *rts = Test_LOGICA_3FPWM_M->childSfunctions[0];
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sfcnOutputs(rts,0);
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}
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/* user code (Output function Trailer) */
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{
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}
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/* Update absolute time for base rate */
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/* The "clockTick0" counts the number of times the code of this task has
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* been executed. The absolute time is the multiplication of "clockTick0"
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* and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
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* overflow during the application lifespan selected.
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* Timer of this task consists of two 32 bit unsigned integers.
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* The two integers represent the low bits Timing.clockTick0 and the high bits
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* Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
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*/
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if (!(++Test_LOGICA_3FPWM_M->Timing.clockTick0)) {
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++Test_LOGICA_3FPWM_M->Timing.clockTickH0;
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}
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Test_LOGICA_3FPWM_M->Timing.t[0] = Test_LOGICA_3FPWM_M->Timing.clockTick0 *
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Test_LOGICA_3FPWM_M->Timing.stepSize0 +
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Test_LOGICA_3FPWM_M->Timing.clockTickH0 *
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Test_LOGICA_3FPWM_M->Timing.stepSize0 * 4294967296.0;
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}
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/* Model initialize function */
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void Test_LOGICA_3FPWM_initialize(void)
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{
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/* Registration code */
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/* initialize non-finites */
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rt_InitInfAndNaN(sizeof(real_T));
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rtsiSetSolverName(&Test_LOGICA_3FPWM_M->solverInfo,"FixedStepDiscrete");
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Test_LOGICA_3FPWM_M->solverInfoPtr = (&Test_LOGICA_3FPWM_M->solverInfo);
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/* Initialize timing info */
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{
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int_T *mdlTsMap = Test_LOGICA_3FPWM_M->Timing.sampleTimeTaskIDArray;
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mdlTsMap[0] = 0;
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Test_LOGICA_3FPWM_M->Timing.sampleTimeTaskIDPtr = (&mdlTsMap[0]);
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Test_LOGICA_3FPWM_M->Timing.sampleTimes =
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(&Test_LOGICA_3FPWM_M->Timing.sampleTimesArray[0]);
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Test_LOGICA_3FPWM_M->Timing.offsetTimes =
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(&Test_LOGICA_3FPWM_M->Timing.offsetTimesArray[0]);
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/* task periods */
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Test_LOGICA_3FPWM_M->Timing.sampleTimes[0] = (5.0E-5);
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/* task offsets */
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Test_LOGICA_3FPWM_M->Timing.offsetTimes[0] = (0.0);
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}
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rtmSetTPtr(Test_LOGICA_3FPWM_M, &Test_LOGICA_3FPWM_M->Timing.tArray[0]);
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{
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int_T *mdlSampleHits = Test_LOGICA_3FPWM_M->Timing.sampleHitArray;
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mdlSampleHits[0] = 1;
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Test_LOGICA_3FPWM_M->Timing.sampleHits = (&mdlSampleHits[0]);
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}
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rtmSetTFinal(Test_LOGICA_3FPWM_M, -1);
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Test_LOGICA_3FPWM_M->Timing.stepSize0 = 5.0E-5;
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Test_LOGICA_3FPWM_M->solverInfoPtr = (&Test_LOGICA_3FPWM_M->solverInfo);
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Test_LOGICA_3FPWM_M->Timing.stepSize = (5.0E-5);
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rtsiSetFixedStepSize(&Test_LOGICA_3FPWM_M->solverInfo, 5.0E-5);
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rtsiSetSolverMode(&Test_LOGICA_3FPWM_M->solverInfo, SOLVER_MODE_SINGLETASKING);
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/* block I/O */
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(void) std::memset((static_cast<void *>(&Test_LOGICA_3FPWM_B)), 0,
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sizeof(B_Test_LOGICA_3FPWM_T));
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/* states (dwork) */
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(void) std::memset(static_cast<void *>(&Test_LOGICA_3FPWM_DW), 0,
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sizeof(DW_Test_LOGICA_3FPWM_T));
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/* child S-Function registration */
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{
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RTWSfcnInfo *sfcnInfo = &Test_LOGICA_3FPWM_M->NonInlinedSFcns.sfcnInfo;
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Test_LOGICA_3FPWM_M->sfcnInfo = (sfcnInfo);
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rtssSetErrorStatusPtr(sfcnInfo, (&rtmGetErrorStatus(Test_LOGICA_3FPWM_M)));
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Test_LOGICA_3FPWM_M->Sizes.numSampTimes = (1);
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rtssSetNumRootSampTimesPtr(sfcnInfo,
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&Test_LOGICA_3FPWM_M->Sizes.numSampTimes);
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Test_LOGICA_3FPWM_M->NonInlinedSFcns.taskTimePtrs[0] = (&rtmGetTPtr
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(Test_LOGICA_3FPWM_M)[0]);
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rtssSetTPtrPtr(sfcnInfo,Test_LOGICA_3FPWM_M->NonInlinedSFcns.taskTimePtrs);
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rtssSetTStartPtr(sfcnInfo, &rtmGetTStart(Test_LOGICA_3FPWM_M));
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rtssSetTFinalPtr(sfcnInfo, &rtmGetTFinal(Test_LOGICA_3FPWM_M));
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rtssSetTimeOfLastOutputPtr(sfcnInfo, &rtmGetTimeOfLastOutput
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(Test_LOGICA_3FPWM_M));
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rtssSetStepSizePtr(sfcnInfo, &Test_LOGICA_3FPWM_M->Timing.stepSize);
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rtssSetStopRequestedPtr(sfcnInfo, &rtmGetStopRequested(Test_LOGICA_3FPWM_M));
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rtssSetDerivCacheNeedsResetPtr(sfcnInfo,
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&Test_LOGICA_3FPWM_M->derivCacheNeedsReset);
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rtssSetZCCacheNeedsResetPtr(sfcnInfo,
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&Test_LOGICA_3FPWM_M->zCCacheNeedsReset);
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rtssSetContTimeOutputInconsistentWithStateAtMajorStepPtr(sfcnInfo,
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&Test_LOGICA_3FPWM_M->CTOutputIncnstWithState);
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rtssSetSampleHitsPtr(sfcnInfo, &Test_LOGICA_3FPWM_M->Timing.sampleHits);
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rtssSetPerTaskSampleHitsPtr(sfcnInfo,
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&Test_LOGICA_3FPWM_M->Timing.perTaskSampleHits);
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rtssSetSimModePtr(sfcnInfo, &Test_LOGICA_3FPWM_M->simMode);
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rtssSetSolverInfoPtr(sfcnInfo, &Test_LOGICA_3FPWM_M->solverInfoPtr);
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}
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Test_LOGICA_3FPWM_M->Sizes.numSFcns = (1);
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/* register each child */
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{
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(void) std::memset(static_cast<void *>
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(&Test_LOGICA_3FPWM_M->NonInlinedSFcns.childSFunctions[0]),
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0,
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1*sizeof(SimStruct));
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Test_LOGICA_3FPWM_M->childSfunctions =
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(&Test_LOGICA_3FPWM_M->NonInlinedSFcns.childSFunctionPtrs[0]);
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Test_LOGICA_3FPWM_M->childSfunctions[0] =
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(&Test_LOGICA_3FPWM_M->NonInlinedSFcns.childSFunctions[0]);
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/* Level2 S-Function Block: Test_LOGICA_3FPWM/<Root>/Digital output (sg_fpga_do_sf_a2) */
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{
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SimStruct *rts = Test_LOGICA_3FPWM_M->childSfunctions[0];
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/* timing info */
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time_T *sfcnPeriod = Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.sfcnPeriod;
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time_T *sfcnOffset = Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.sfcnOffset;
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int_T *sfcnTsMap = Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.sfcnTsMap;
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(void) std::memset(static_cast<void*>(sfcnPeriod), 0,
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sizeof(time_T)*1);
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(void) std::memset(static_cast<void*>(sfcnOffset), 0,
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sizeof(time_T)*1);
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ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
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ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
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ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
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{
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ssSetBlkInfo2Ptr(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.blkInfo2[0]);
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}
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_ssSetBlkInfo2PortInfo2Ptr(rts,
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&Test_LOGICA_3FPWM_M->NonInlinedSFcns.inputOutputPortInfo2[0]);
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/* Set up the mdlInfo pointer */
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ssSetRTWSfcnInfo(rts, Test_LOGICA_3FPWM_M->sfcnInfo);
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/* Allocate memory of model methods 2 */
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{
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ssSetModelMethods2(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.methods2[0]);
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}
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/* Allocate memory of model methods 3 */
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{
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ssSetModelMethods3(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.methods3[0]);
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}
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/* Allocate memory of model methods 4 */
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{
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ssSetModelMethods4(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.methods4[0]);
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}
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/* Allocate memory for states auxilliary information */
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{
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ssSetStatesInfo2(rts, &Test_LOGICA_3FPWM_M->NonInlinedSFcns.statesInfo2
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[0]);
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ssSetPeriodicStatesInfo(rts,
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&Test_LOGICA_3FPWM_M->NonInlinedSFcns.periodicStatesInfo[0]);
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}
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/* inputs */
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{
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_ssSetNumInputPorts(rts, 6);
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ssSetPortInfoForInputs(rts,
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&Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
|
|
ssSetPortInfoForInputs(rts,
|
|
&Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
|
|
_ssSetPortInfo2ForInputUnits(rts,
|
|
&Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.inputPortUnits[0]);
|
|
ssSetInputPortUnit(rts, 0, 0);
|
|
ssSetInputPortUnit(rts, 1, 0);
|
|
ssSetInputPortUnit(rts, 2, 0);
|
|
ssSetInputPortUnit(rts, 3, 0);
|
|
ssSetInputPortUnit(rts, 4, 0);
|
|
ssSetInputPortUnit(rts, 5, 0);
|
|
_ssSetPortInfo2ForInputCoSimAttribute(rts,
|
|
&Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.inputPortCoSimAttribute[0]);
|
|
ssSetInputPortIsContinuousQuantity(rts, 0, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 1, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 2, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 3, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 4, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 5, 0);
|
|
|
|
/* port 0 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 0, 1);
|
|
ssSetInputPortSignal(rts, 0, &Test_LOGICA_3FPWM_B.DataTypeConversion[0]);
|
|
_ssSetInputPortNumDimensions(rts, 0, 1);
|
|
ssSetInputPortWidthAsInt(rts, 0, 1);
|
|
}
|
|
|
|
/* port 1 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 1, 1);
|
|
ssSetInputPortSignal(rts, 1, &Test_LOGICA_3FPWM_B.DataTypeConversion[1]);
|
|
_ssSetInputPortNumDimensions(rts, 1, 1);
|
|
ssSetInputPortWidthAsInt(rts, 1, 1);
|
|
}
|
|
|
|
/* port 2 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 2, 1);
|
|
ssSetInputPortSignal(rts, 2, &Test_LOGICA_3FPWM_B.DataTypeConversion[2]);
|
|
_ssSetInputPortNumDimensions(rts, 2, 1);
|
|
ssSetInputPortWidthAsInt(rts, 2, 1);
|
|
}
|
|
|
|
/* port 3 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 3, 1);
|
|
ssSetInputPortSignal(rts, 3, &Test_LOGICA_3FPWM_B.DataTypeConversion[3]);
|
|
_ssSetInputPortNumDimensions(rts, 3, 1);
|
|
ssSetInputPortWidthAsInt(rts, 3, 1);
|
|
}
|
|
|
|
/* port 4 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 4, 1);
|
|
ssSetInputPortSignal(rts, 4, &Test_LOGICA_3FPWM_B.DataTypeConversion[4]);
|
|
_ssSetInputPortNumDimensions(rts, 4, 1);
|
|
ssSetInputPortWidthAsInt(rts, 4, 1);
|
|
}
|
|
|
|
/* port 5 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 5, 1);
|
|
ssSetInputPortSignal(rts, 5, &Test_LOGICA_3FPWM_B.DataTypeConversion[5]);
|
|
_ssSetInputPortNumDimensions(rts, 5, 1);
|
|
ssSetInputPortWidthAsInt(rts, 5, 1);
|
|
}
|
|
}
|
|
|
|
/* path info */
|
|
ssSetModelName(rts, "Digital output");
|
|
ssSetPath(rts, "Test_LOGICA_3FPWM/Digital output");
|
|
ssSetRTModel(rts,Test_LOGICA_3FPWM_M);
|
|
ssSetParentSS(rts, (NULL));
|
|
ssSetRootSS(rts, rts);
|
|
ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
|
|
|
|
/* parameters */
|
|
{
|
|
mxArray **sfcnParams = (mxArray **)
|
|
&Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.params;
|
|
ssSetSFcnParamsCount(rts, 6);
|
|
ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
|
|
ssSetSFcnParam(rts, 0, (mxArray*)
|
|
Test_LOGICA_3FPWM_cal->Digitaloutput_P1_Size);
|
|
ssSetSFcnParam(rts, 1, (mxArray*)
|
|
Test_LOGICA_3FPWM_cal->Digitaloutput_P2_Size);
|
|
ssSetSFcnParam(rts, 2, (mxArray*)
|
|
Test_LOGICA_3FPWM_cal->Digitaloutput_P3_Size);
|
|
ssSetSFcnParam(rts, 3, (mxArray*)
|
|
Test_LOGICA_3FPWM_cal->Digitaloutput_P4_Size);
|
|
ssSetSFcnParam(rts, 4, (mxArray*)
|
|
Test_LOGICA_3FPWM_cal->Digitaloutput_P5_Size);
|
|
ssSetSFcnParam(rts, 5, (mxArray*)
|
|
Test_LOGICA_3FPWM_cal->Digitaloutput_P6_Size);
|
|
}
|
|
|
|
/* work vectors */
|
|
ssSetIWork(rts, (int_T *) &Test_LOGICA_3FPWM_DW.Digitaloutput_IWORK);
|
|
ssSetPWork(rts, (void **) &Test_LOGICA_3FPWM_DW.Digitaloutput_PWORK[0]);
|
|
|
|
{
|
|
struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
|
|
&Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.dWork;
|
|
struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
|
|
&Test_LOGICA_3FPWM_M->NonInlinedSFcns.Sfcn0.dWorkAux;
|
|
ssSetSFcnDWork(rts, dWorkRecord);
|
|
ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
|
|
ssSetNumDWorkAsInt(rts, 2);
|
|
|
|
/* IWORK */
|
|
ssSetDWorkWidthAsInt(rts, 0, 1);
|
|
ssSetDWorkDataType(rts, 0,SS_INTEGER);
|
|
ssSetDWorkComplexSignal(rts, 0, 0);
|
|
ssSetDWork(rts, 0, &Test_LOGICA_3FPWM_DW.Digitaloutput_IWORK);
|
|
|
|
/* PWORK */
|
|
ssSetDWorkWidthAsInt(rts, 1, 2);
|
|
ssSetDWorkDataType(rts, 1,SS_POINTER);
|
|
ssSetDWorkComplexSignal(rts, 1, 0);
|
|
ssSetDWork(rts, 1, &Test_LOGICA_3FPWM_DW.Digitaloutput_PWORK[0]);
|
|
}
|
|
|
|
/* registration */
|
|
sg_fpga_do_sf_a2(rts);
|
|
sfcnInitializeSizes(rts);
|
|
sfcnInitializeSampleTimes(rts);
|
|
|
|
/* adjust sample time */
|
|
ssSetSampleTime(rts, 0, 5.0E-5);
|
|
ssSetOffsetTime(rts, 0, 0.0);
|
|
sfcnTsMap[0] = 0;
|
|
|
|
/* set compiled values of dynamic vector attributes */
|
|
ssSetNumNonsampledZCsAsInt(rts, 0);
|
|
|
|
/* Update connectivity flags for each port */
|
|
_ssSetInputPortConnected(rts, 0, 1);
|
|
_ssSetInputPortConnected(rts, 1, 1);
|
|
_ssSetInputPortConnected(rts, 2, 1);
|
|
_ssSetInputPortConnected(rts, 3, 1);
|
|
_ssSetInputPortConnected(rts, 4, 1);
|
|
_ssSetInputPortConnected(rts, 5, 1);
|
|
|
|
/* Update the BufferDstPort flags for each input port */
|
|
ssSetInputPortBufferDstPort(rts, 0, -1);
|
|
ssSetInputPortBufferDstPort(rts, 1, -1);
|
|
ssSetInputPortBufferDstPort(rts, 2, -1);
|
|
ssSetInputPortBufferDstPort(rts, 3, -1);
|
|
ssSetInputPortBufferDstPort(rts, 4, -1);
|
|
ssSetInputPortBufferDstPort(rts, 5, -1);
|
|
}
|
|
}
|
|
|
|
/* Start for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
|
|
/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = Test_LOGICA_3FPWM_M->childSfunctions[0];
|
|
sfcnStart(rts);
|
|
if (ssGetErrorStatus(rts) != (NULL))
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Model terminate function */
|
|
void Test_LOGICA_3FPWM_terminate(void)
|
|
{
|
|
/* Terminate for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
|
|
/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = Test_LOGICA_3FPWM_M->childSfunctions[0];
|
|
sfcnTerminate(rts);
|
|
}
|
|
|
|
/* user code (Terminate function Trailer) */
|
|
{
|
|
freeFPGAModuleSgLib((uint32_t)1);
|
|
}
|
|
}
|