1263 lines
45 KiB
C++
1263 lines
45 KiB
C++
/*
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* control_Velocidad.cpp
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*
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* Academic License - for use in teaching, academic research, and meeting
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* course requirements at degree granting institutions only. Not for
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* government, commercial, or other organizational use.
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*
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* Code generation for model "control_Velocidad".
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*
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* Model version : 1.53
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* Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
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* C++ source code generated on : Fri Aug 22 13:33:37 2025
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*
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* Target selection: speedgoat.tlc
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* Note: GRT includes extra infrastructure and instrumentation for prototyping
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* Embedded hardware selection: Intel->x86-64 (Linux 64)
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* Code generation objectives: Unspecified
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* Validation result: Not run
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*/
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#include "control_Velocidad.h"
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#include "control_Velocidad_cal.h"
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#include "rtwtypes.h"
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#include "rte_control_Velocidad_parameters.h"
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#include <cmath>
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#include "control_Velocidad_private.h"
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#include "zero_crossing_types.h"
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#include <cstring>
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extern "C"
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{
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#include "rt_nonfinite.h"
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}
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#include <cfloat>
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/* Block signals (default storage) */
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B_control_Velocidad_T control_Velocidad_B;
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/* Continuous states */
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X_control_Velocidad_T control_Velocidad_X;
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/* Disabled State Vector */
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XDis_control_Velocidad_T control_Velocidad_XDis;
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/* Block states (default storage) */
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DW_control_Velocidad_T control_Velocidad_DW;
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/* Previous zero-crossings (trigger) states */
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PrevZCX_control_Velocidad_T control_Velocidad_PrevZCX;
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/* Real-time model */
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RT_MODEL_control_Velocidad_T control_Velocidad_M_ = RT_MODEL_control_Velocidad_T
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();
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RT_MODEL_control_Velocidad_T *const control_Velocidad_M = &control_Velocidad_M_;
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/*
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* This function updates continuous states using the ODE3 fixed-step
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* solver algorithm
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*/
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static void rt_ertODEUpdateContinuousStates(RTWSolverInfo *si )
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{
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/* Solver Matrices */
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static const real_T rt_ODE3_A[3] = {
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1.0/2.0, 3.0/4.0, 1.0
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};
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static const real_T rt_ODE3_B[3][3] = {
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{ 1.0/2.0, 0.0, 0.0 },
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{ 0.0, 3.0/4.0, 0.0 },
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{ 2.0/9.0, 1.0/3.0, 4.0/9.0 }
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};
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time_T t = rtsiGetT(si);
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time_T tnew = rtsiGetSolverStopTime(si);
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time_T h = rtsiGetStepSize(si);
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real_T *x = rtsiGetContStates(si);
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ODE3_IntgData *id = static_cast<ODE3_IntgData *>(rtsiGetSolverData(si));
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real_T *y = id->y;
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real_T *f0 = id->f[0];
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real_T *f1 = id->f[1];
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real_T *f2 = id->f[2];
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real_T hB[3];
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int_T i;
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int_T nXc = 1;
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rtsiSetSimTimeStep(si,MINOR_TIME_STEP);
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/* Save the state values at time t in y, we'll use x as ynew. */
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(void) std::memcpy(y, x,
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static_cast<uint_T>(nXc)*sizeof(real_T));
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/* Assumes that rtsiSetT and ModelOutputs are up-to-date */
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/* f0 = f(t,y) */
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rtsiSetdX(si, f0);
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control_Velocidad_derivatives();
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/* f(:,2) = feval(odefile, t + hA(1), y + f*hB(:,1), args(:)(*)); */
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hB[0] = h * rt_ODE3_B[0][0];
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for (i = 0; i < nXc; i++) {
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x[i] = y[i] + (f0[i]*hB[0]);
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}
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rtsiSetT(si, t + h*rt_ODE3_A[0]);
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rtsiSetdX(si, f1);
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control_Velocidad_step();
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control_Velocidad_derivatives();
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/* f(:,3) = feval(odefile, t + hA(2), y + f*hB(:,2), args(:)(*)); */
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for (i = 0; i <= 1; i++) {
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hB[i] = h * rt_ODE3_B[1][i];
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}
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for (i = 0; i < nXc; i++) {
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x[i] = y[i] + (f0[i]*hB[0] + f1[i]*hB[1]);
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}
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rtsiSetT(si, t + h*rt_ODE3_A[1]);
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rtsiSetdX(si, f2);
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control_Velocidad_step();
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control_Velocidad_derivatives();
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/* tnew = t + hA(3);
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ynew = y + f*hB(:,3); */
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for (i = 0; i <= 2; i++) {
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hB[i] = h * rt_ODE3_B[2][i];
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}
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for (i = 0; i < nXc; i++) {
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x[i] = y[i] + (f0[i]*hB[0] + f1[i]*hB[1] + f2[i]*hB[2]);
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}
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rtsiSetT(si, tnew);
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rtsiSetSimTimeStep(si,MAJOR_TIME_STEP);
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}
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real_T rt_remd_snf(real_T u0, real_T u1)
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{
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real_T y;
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if (rtIsNaN(u0) || rtIsNaN(u1) || rtIsInf(u0)) {
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y = (rtNaN);
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} else if (rtIsInf(u1)) {
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y = u0;
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} else {
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if (u1 < 0.0) {
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y = std::ceil(u1);
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} else {
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y = std::floor(u1);
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}
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if ((u1 != 0.0) && (u1 != y)) {
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real_T q;
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q = std::abs(u0 / u1);
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if (!(std::abs(q - std::floor(q + 0.5)) > DBL_EPSILON * q)) {
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y = 0.0 * u0;
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} else {
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y = std::fmod(u0, u1);
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}
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} else {
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y = std::fmod(u0, u1);
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}
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}
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return y;
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}
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/* Model step function */
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void control_Velocidad_step(void)
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{
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if (rtmIsMajorTimeStep(control_Velocidad_M)) {
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/* set solver stop time */
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if (!(control_Velocidad_M->Timing.clockTick0+1)) {
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rtsiSetSolverStopTime(&control_Velocidad_M->solverInfo,
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((control_Velocidad_M->Timing.clockTickH0 + 1) *
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control_Velocidad_M->Timing.stepSize0 * 4294967296.0));
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} else {
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rtsiSetSolverStopTime(&control_Velocidad_M->solverInfo,
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((control_Velocidad_M->Timing.clockTick0 + 1) *
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control_Velocidad_M->Timing.stepSize0 +
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control_Velocidad_M->Timing.clockTickH0 *
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control_Velocidad_M->Timing.stepSize0 * 4294967296.0));
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}
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} /* end MajorTimeStep */
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/* Update absolute time of base rate at minor time step */
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if (rtmIsMinorTimeStep(control_Velocidad_M)) {
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control_Velocidad_M->Timing.t[0] = rtsiGetT(&control_Velocidad_M->solverInfo);
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}
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{
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real_T u0;
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real_T u1;
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real_T u2;
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boolean_T tmp;
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boolean_T zcEvent;
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/* Reset subsysRan breadcrumbs */
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srClearBC(control_Velocidad_DW.TriggeredSubsystem_SubsysRanBC);
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/* Reset subsysRan breadcrumbs */
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srClearBC(control_Velocidad_DW.NEGATIVEEdge_SubsysRanBC);
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/* Reset subsysRan breadcrumbs */
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srClearBC(control_Velocidad_DW.POSITIVEEdge_SubsysRanBC);
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/* Outputs for Enabled SubSystem: '<S5>/NEGATIVE Edge' incorporates:
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* EnablePort: '<S7>/Enable'
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*/
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tmp = rtmIsMajorTimeStep(control_Velocidad_M);
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/* End of Outputs for SubSystem: '<S5>/NEGATIVE Edge' */
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if (tmp) {
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/* Gain: '<Root>/Gain1' */
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u0 = *get_polos() / 120.0;
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/* Gain: '<Root>/Gain1' incorporates:
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* Constant: '<Root>/Constant1'
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*/
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control_Velocidad_B.Gain1 = u0 * control_Velocidad_cal->Constant1_Value;
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/* Abs: '<Root>/Abs' */
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control_Velocidad_B.Abs = std::abs(control_Velocidad_B.Gain1);
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/* Gain: '<Root>/CTE_amplitud' */
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control_Velocidad_B.CTE_amplitud = *get_cte_amplitud() *
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control_Velocidad_B.Abs;
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/* Saturate: '<Root>/Saturation' */
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u0 = control_Velocidad_B.CTE_amplitud;
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u1 = control_Velocidad_cal->Saturation_LowerSat;
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u2 = control_Velocidad_cal->Saturation_UpperSat;
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if (u0 > u2) {
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/* Saturate: '<Root>/Saturation' */
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control_Velocidad_B.Saturation = u2;
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} else if (u0 < u1) {
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/* Saturate: '<Root>/Saturation' */
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control_Velocidad_B.Saturation = u1;
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} else {
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/* Saturate: '<Root>/Saturation' */
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control_Velocidad_B.Saturation = u0;
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}
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/* End of Saturate: '<Root>/Saturation' */
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/* DiscreteIntegrator: '<S2>/Discrete-Time Integrator' */
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control_Velocidad_B.DiscreteTimeIntegrator =
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control_Velocidad_DW.DiscreteTimeIntegrator_DSTATE;
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/* Trigonometry: '<S2>/Trigonometric Function' */
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control_Velocidad_B.TrigonometricFunction = std::sin
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(control_Velocidad_B.DiscreteTimeIntegrator);
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/* Sum: '<S2>/Sum' incorporates:
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* Constant: '<S2>/Constant1'
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*/
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control_Velocidad_B.Sum = control_Velocidad_B.DiscreteTimeIntegrator +
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control_Velocidad_cal->Constant1_Value_l;
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/* Trigonometry: '<S2>/Trigonometric Function1' */
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control_Velocidad_B.TrigonometricFunction1 = std::sin
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(control_Velocidad_B.Sum);
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/* Sum: '<S2>/Sum1' incorporates:
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* Constant: '<S2>/Constant2'
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*/
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control_Velocidad_B.Sum1 = control_Velocidad_B.DiscreteTimeIntegrator +
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control_Velocidad_cal->Constant2_Value;
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/* Trigonometry: '<S2>/Trigonometric Function2' */
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control_Velocidad_B.TrigonometricFunction2 = std::sin
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(control_Velocidad_B.Sum1);
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/* Product: '<Root>/Product' */
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control_Velocidad_B.Product[0] = control_Velocidad_B.Saturation *
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control_Velocidad_B.TrigonometricFunction;
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control_Velocidad_B.Product[1] = control_Velocidad_B.Saturation *
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control_Velocidad_B.TrigonometricFunction1;
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control_Velocidad_B.Product[2] = control_Velocidad_B.Saturation *
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control_Velocidad_B.TrigonometricFunction2;
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/* DigitalClock: '<S11>/Digital Clock' */
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control_Velocidad_B.DigitalClock = control_Velocidad_M->Timing.t[1];
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/* Sum: '<S11>/Add1' incorporates:
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* Constant: '<S11>/Constant3'
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*/
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control_Velocidad_B.Add1 = control_Velocidad_B.DigitalClock +
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control_Velocidad_cal->Constant3_Value;
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/* Math: '<S11>/Math Function' incorporates:
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* Constant: '<S11>/Constant2'
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*/
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control_Velocidad_B.MathFunction = rt_remd_snf(control_Velocidad_B.Add1,
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control_Velocidad_cal->Constant2_Value_d);
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/* Gain: '<S11>/1\ib1' */
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control_Velocidad_B.uib1 = control_Velocidad_cal->uib1_Gain *
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control_Velocidad_B.MathFunction;
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/* Fcn: '<S11>/Fcn' */
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control_Velocidad_B.Fcn = 2.0 * control_Velocidad_B.uib1 - 1.0;
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/* RelationalOperator: '<S3>/Relational Operator' */
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control_Velocidad_B.RelationalOperator[0] = (control_Velocidad_B.Product[0]
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>= control_Velocidad_B.Fcn);
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control_Velocidad_B.RelationalOperator[1] = (control_Velocidad_B.Product[1]
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>= control_Velocidad_B.Fcn);
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control_Velocidad_B.RelationalOperator[2] = (control_Velocidad_B.Product[2]
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>= control_Velocidad_B.Fcn);
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/* Logic: '<S3>/Logical Operator' */
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control_Velocidad_B.LogicalOperator =
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!control_Velocidad_B.RelationalOperator[0];
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/* Logic: '<S3>/Logical Operator1' */
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control_Velocidad_B.LogicalOperator1 =
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!control_Velocidad_B.RelationalOperator[1];
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/* Logic: '<S3>/Logical Operator2' */
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control_Velocidad_B.LogicalOperator2 =
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!control_Velocidad_B.RelationalOperator[2];
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/* DataTypeConversion: '<S3>/Cast To Double' */
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control_Velocidad_B.CastToDouble[0] =
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control_Velocidad_B.RelationalOperator[0];
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control_Velocidad_B.CastToDouble[1] = control_Velocidad_B.LogicalOperator;
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control_Velocidad_B.CastToDouble[2] =
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control_Velocidad_B.RelationalOperator[1];
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control_Velocidad_B.CastToDouble[3] = control_Velocidad_B.LogicalOperator1;
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control_Velocidad_B.CastToDouble[4] =
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control_Velocidad_B.RelationalOperator[2];
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control_Velocidad_B.CastToDouble[5] = control_Velocidad_B.LogicalOperator2;
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/* S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
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/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
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{
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SimStruct *rts = control_Velocidad_M->childSfunctions[0];
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sfcnOutputs(rts,0);
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}
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/* Gain: '<S2>/Gain' */
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control_Velocidad_B.Gain = control_Velocidad_cal->Gain_Gain *
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control_Velocidad_B.Gain1;
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/* S-Function (sg_fpga_di_sf_a2): '<Root>/Digital input' */
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/* Level2 S-Function Block: '<Root>/Digital input' (sg_fpga_di_sf_a2) */
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{
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SimStruct *rts = control_Velocidad_M->childSfunctions[1];
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sfcnOutputs(rts,0);
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}
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/* Memory: '<S5>/Memory' */
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control_Velocidad_B.Memory = control_Velocidad_DW.Memory_PreviousInput;
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/* MultiPortSwitch: '<S5>/Multiport Switch' incorporates:
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* Constant: '<S5>/Constant1'
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*/
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switch (static_cast<int32_T>(control_Velocidad_cal->EdgeDetector_model)) {
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case 1:
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/* MultiPortSwitch: '<S5>/Multiport Switch' incorporates:
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* Constant: '<S5>/pos. edge'
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*/
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control_Velocidad_B.MultiportSwitch[0] =
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control_Velocidad_cal->posedge_Value[0];
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control_Velocidad_B.MultiportSwitch[1] =
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control_Velocidad_cal->posedge_Value[1];
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break;
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case 2:
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/* MultiPortSwitch: '<S5>/Multiport Switch' incorporates:
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* Constant: '<S5>/neg. edge'
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*/
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control_Velocidad_B.MultiportSwitch[0] =
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control_Velocidad_cal->negedge_Value[0];
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control_Velocidad_B.MultiportSwitch[1] =
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control_Velocidad_cal->negedge_Value[1];
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break;
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default:
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/* MultiPortSwitch: '<S5>/Multiport Switch' incorporates:
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* Constant: '<S5>/either edge'
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*/
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control_Velocidad_B.MultiportSwitch[0] =
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control_Velocidad_cal->eitheredge_Value[0];
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control_Velocidad_B.MultiportSwitch[1] =
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control_Velocidad_cal->eitheredge_Value[1];
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break;
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}
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/* End of MultiPortSwitch: '<S5>/Multiport Switch' */
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/* Outputs for Enabled SubSystem: '<S5>/POSITIVE Edge' incorporates:
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* EnablePort: '<S8>/Enable'
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*/
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if (rtsiIsModeUpdateTimeStep(&control_Velocidad_M->solverInfo)) {
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control_Velocidad_DW.POSITIVEEdge_MODE =
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(control_Velocidad_B.MultiportSwitch[0] > 0.0);
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}
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/* End of Outputs for SubSystem: '<S5>/POSITIVE Edge' */
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}
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/* DataTypeConversion: '<S5>/Data Type Conversion2' */
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control_Velocidad_B.DataTypeConversion2 =
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(control_Velocidad_B.Digitalinput_o1 != 0.0);
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/* Outputs for Enabled SubSystem: '<S5>/POSITIVE Edge' incorporates:
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* EnablePort: '<S8>/Enable'
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*/
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if (control_Velocidad_DW.POSITIVEEdge_MODE) {
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/* RelationalOperator: '<S8>/Relational Operator1' */
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control_Velocidad_B.RelationalOperator1 = (static_cast<int32_T>
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(control_Velocidad_B.Memory) < static_cast<int32_T>
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(control_Velocidad_B.DataTypeConversion2));
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if (rtsiIsModeUpdateTimeStep(&control_Velocidad_M->solverInfo)) {
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srUpdateBC(control_Velocidad_DW.POSITIVEEdge_SubsysRanBC);
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}
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}
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/* End of Outputs for SubSystem: '<S5>/POSITIVE Edge' */
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/* Outputs for Enabled SubSystem: '<S5>/NEGATIVE Edge' incorporates:
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* EnablePort: '<S7>/Enable'
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*/
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if (tmp && rtsiIsModeUpdateTimeStep(&control_Velocidad_M->solverInfo)) {
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control_Velocidad_DW.NEGATIVEEdge_MODE =
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(control_Velocidad_B.MultiportSwitch[1] > 0.0);
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}
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if (control_Velocidad_DW.NEGATIVEEdge_MODE) {
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/* RelationalOperator: '<S7>/Relational Operator1' */
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control_Velocidad_B.RelationalOperator1_e = (static_cast<int32_T>
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(control_Velocidad_B.Memory) > static_cast<int32_T>
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(control_Velocidad_B.DataTypeConversion2));
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if (rtsiIsModeUpdateTimeStep(&control_Velocidad_M->solverInfo)) {
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srUpdateBC(control_Velocidad_DW.NEGATIVEEdge_SubsysRanBC);
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}
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}
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|
|
/* End of Outputs for SubSystem: '<S5>/NEGATIVE Edge' */
|
|
|
|
/* Logic: '<S5>/Logical Operator1' */
|
|
control_Velocidad_B.LogicalOperator1_g =
|
|
(control_Velocidad_B.RelationalOperator1 ||
|
|
control_Velocidad_B.RelationalOperator1_e);
|
|
|
|
/* DataTypeConversion: '<S1>/Data Type Conversion' */
|
|
control_Velocidad_B.DataTypeConversion =
|
|
control_Velocidad_B.LogicalOperator1_g;
|
|
if (tmp) {
|
|
/* Delay: '<S1>/Delay4' */
|
|
control_Velocidad_B.Delay4 = control_Velocidad_DW.Delay4_DSTATE;
|
|
|
|
/* Delay: '<S1>/Delay3' */
|
|
control_Velocidad_B.Delay3 = control_Velocidad_DW.Delay3_DSTATE[0];
|
|
}
|
|
|
|
/* Switch: '<S1>/Switch1' */
|
|
if (control_Velocidad_B.Delay3 > *get_n_lim_direccion()) {
|
|
/* Switch: '<S1>/Switch1' */
|
|
control_Velocidad_B.Switch1 = control_Velocidad_B.Delay4;
|
|
} else {
|
|
/* Logic: '<S1>/Logical Operator' */
|
|
control_Velocidad_B.LogicalOperator_g =
|
|
(control_Velocidad_B.LogicalOperator1_g &&
|
|
(control_Velocidad_B.Digitalinput_o2 != 0.0));
|
|
|
|
/* Switch: '<S1>/Switch1' */
|
|
control_Velocidad_B.Switch1 = control_Velocidad_B.LogicalOperator_g;
|
|
}
|
|
|
|
/* End of Switch: '<S1>/Switch1' */
|
|
|
|
/* Switch: '<S1>/Switch' */
|
|
if (control_Velocidad_B.Switch1) {
|
|
/* Switch: '<S1>/Switch' */
|
|
control_Velocidad_B.Switch = control_Velocidad_B.DataTypeConversion;
|
|
} else {
|
|
/* Gain: '<S1>/Gain1' */
|
|
control_Velocidad_B.Gain1_h = control_Velocidad_cal->Gain1_Gain *
|
|
control_Velocidad_B.DataTypeConversion;
|
|
|
|
/* Switch: '<S1>/Switch' */
|
|
control_Velocidad_B.Switch = control_Velocidad_B.Gain1_h;
|
|
}
|
|
|
|
/* End of Switch: '<S1>/Switch' */
|
|
if (tmp) {
|
|
/* Delay: '<S1>/Delay1' */
|
|
control_Velocidad_B.Delay1 = control_Velocidad_DW.Delay1_DSTATE;
|
|
}
|
|
|
|
/* Sum: '<S1>/Sum' */
|
|
control_Velocidad_B.Sum_l = control_Velocidad_B.Switch +
|
|
control_Velocidad_B.Delay1;
|
|
|
|
/* Gain: '<S1>/CTE Encoder' */
|
|
control_Velocidad_B.CTEEncoder = *get_cte_encoder() *
|
|
control_Velocidad_B.Sum_l;
|
|
|
|
/* TransferFcn: '<S1>/Filtro Pasa Baja' */
|
|
control_Velocidad_B.FiltroPasaBaja = 0.0;
|
|
control_Velocidad_B.FiltroPasaBaja +=
|
|
control_Velocidad_cal->FiltroPasaBaja_C *
|
|
control_Velocidad_X.FiltroPasaBaja_CSTATE;
|
|
if (tmp) {
|
|
/* Delay: '<S1>/Delay' */
|
|
control_Velocidad_B.Delay = control_Velocidad_DW.Delay_DSTATE[0];
|
|
}
|
|
|
|
/* Abs: '<S1>/Abs1' */
|
|
control_Velocidad_B.Abs1 = std::abs(control_Velocidad_B.FiltroPasaBaja);
|
|
|
|
/* Clock: '<S6>/Clock' */
|
|
control_Velocidad_B.Clock = control_Velocidad_M->Timing.t[0];
|
|
if (tmp) {
|
|
/* Outputs for Triggered SubSystem: '<S6>/Triggered Subsystem' incorporates:
|
|
* TriggerPort: '<S9>/Trigger'
|
|
*/
|
|
if (rtsiIsModeUpdateTimeStep(&control_Velocidad_M->solverInfo)) {
|
|
zcEvent = (control_Velocidad_B.LogicalOperator1_g &&
|
|
(control_Velocidad_PrevZCX.TriggeredSubsystem_Trig_ZCE !=
|
|
POS_ZCSIG));
|
|
if (zcEvent) {
|
|
/* SignalConversion generated from: '<S9>/In1' */
|
|
control_Velocidad_B.In1 = control_Velocidad_B.Clock;
|
|
control_Velocidad_DW.TriggeredSubsystem_SubsysRanBC = 4;
|
|
}
|
|
|
|
control_Velocidad_PrevZCX.TriggeredSubsystem_Trig_ZCE =
|
|
control_Velocidad_B.LogicalOperator1_g;
|
|
}
|
|
|
|
/* End of Outputs for SubSystem: '<S6>/Triggered Subsystem' */
|
|
|
|
/* Sum: '<S6>/Sum' incorporates:
|
|
* Constant: '<S6>/Constant'
|
|
*/
|
|
control_Velocidad_B.Sum_g = control_Velocidad_B.In1 +
|
|
control_Velocidad_cal->Constant_Value;
|
|
}
|
|
|
|
/* RelationalOperator: '<S6>/Relational Operator' */
|
|
control_Velocidad_B.RelationalOperator_k = (control_Velocidad_B.Sum_g >
|
|
control_Velocidad_B.Clock);
|
|
|
|
/* Sum: '<S1>/Sum1' */
|
|
control_Velocidad_B.Sum1_c = control_Velocidad_B.CTEEncoder -
|
|
control_Velocidad_B.Delay;
|
|
|
|
/* Gain: '<S1>/Gain' */
|
|
control_Velocidad_B.Gain_e = *get_gain_velocidad() *
|
|
control_Velocidad_B.Sum1_c;
|
|
if (tmp) {
|
|
}
|
|
|
|
/* user code (Output function Trailer) */
|
|
{
|
|
}
|
|
}
|
|
|
|
if (rtmIsMajorTimeStep(control_Velocidad_M)) {
|
|
int32_T idxDelay;
|
|
if (rtmIsMajorTimeStep(control_Velocidad_M)) {
|
|
/* Update for DiscreteIntegrator: '<S2>/Discrete-Time Integrator' */
|
|
control_Velocidad_DW.DiscreteTimeIntegrator_DSTATE +=
|
|
control_Velocidad_cal->DiscreteTimeIntegrator_gainval *
|
|
control_Velocidad_B.Gain;
|
|
|
|
/* Update for Memory: '<S5>/Memory' */
|
|
control_Velocidad_DW.Memory_PreviousInput =
|
|
control_Velocidad_B.DataTypeConversion2;
|
|
|
|
/* Update for Delay: '<S1>/Delay4' */
|
|
control_Velocidad_DW.Delay4_DSTATE = control_Velocidad_B.Switch1;
|
|
|
|
/* Update for Delay: '<S1>/Delay1' */
|
|
control_Velocidad_DW.Delay1_DSTATE = control_Velocidad_B.Sum_l;
|
|
for (idxDelay = 0; idxDelay < 99; idxDelay++) {
|
|
/* Update for Delay: '<S1>/Delay3' */
|
|
control_Velocidad_DW.Delay3_DSTATE[idxDelay] =
|
|
control_Velocidad_DW.Delay3_DSTATE[idxDelay + 1];
|
|
|
|
/* Update for Delay: '<S1>/Delay' */
|
|
control_Velocidad_DW.Delay_DSTATE[idxDelay] =
|
|
control_Velocidad_DW.Delay_DSTATE[idxDelay + 1];
|
|
}
|
|
|
|
/* Update for Delay: '<S1>/Delay3' */
|
|
control_Velocidad_DW.Delay3_DSTATE[99] = control_Velocidad_B.Abs1;
|
|
|
|
/* Update for Delay: '<S1>/Delay' */
|
|
control_Velocidad_DW.Delay_DSTATE[99] = control_Velocidad_B.CTEEncoder;
|
|
}
|
|
} /* end MajorTimeStep */
|
|
|
|
if (rtmIsMajorTimeStep(control_Velocidad_M)) {
|
|
rt_ertODEUpdateContinuousStates(&control_Velocidad_M->solverInfo);
|
|
|
|
/* Update absolute time for base rate */
|
|
/* The "clockTick0" counts the number of times the code of this task has
|
|
* been executed. The absolute time is the multiplication of "clockTick0"
|
|
* and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
|
|
* overflow during the application lifespan selected.
|
|
* Timer of this task consists of two 32 bit unsigned integers.
|
|
* The two integers represent the low bits Timing.clockTick0 and the high bits
|
|
* Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
|
|
*/
|
|
if (!(++control_Velocidad_M->Timing.clockTick0)) {
|
|
++control_Velocidad_M->Timing.clockTickH0;
|
|
}
|
|
|
|
control_Velocidad_M->Timing.t[0] = rtsiGetSolverStopTime
|
|
(&control_Velocidad_M->solverInfo);
|
|
|
|
{
|
|
/* Update absolute timer for sample time: [5.0E-5s, 0.0s] */
|
|
/* The "clockTick1" counts the number of times the code of this task has
|
|
* been executed. The absolute time is the multiplication of "clockTick1"
|
|
* and "Timing.stepSize1". Size of "clockTick1" ensures timer will not
|
|
* overflow during the application lifespan selected.
|
|
* Timer of this task consists of two 32 bit unsigned integers.
|
|
* The two integers represent the low bits Timing.clockTick1 and the high bits
|
|
* Timing.clockTickH1. When the low bit overflows to 0, the high bits increment.
|
|
*/
|
|
if (!(++control_Velocidad_M->Timing.clockTick1)) {
|
|
++control_Velocidad_M->Timing.clockTickH1;
|
|
}
|
|
|
|
control_Velocidad_M->Timing.t[1] = control_Velocidad_M->Timing.clockTick1 *
|
|
control_Velocidad_M->Timing.stepSize1 +
|
|
control_Velocidad_M->Timing.clockTickH1 *
|
|
control_Velocidad_M->Timing.stepSize1 * 4294967296.0;
|
|
}
|
|
} /* end MajorTimeStep */
|
|
}
|
|
|
|
/* Derivatives for root system: '<Root>' */
|
|
void control_Velocidad_derivatives(void)
|
|
{
|
|
XDot_control_Velocidad_T *_rtXdot;
|
|
_rtXdot = ((XDot_control_Velocidad_T *) control_Velocidad_M->derivs);
|
|
|
|
/* Derivatives for TransferFcn: '<S1>/Filtro Pasa Baja' */
|
|
_rtXdot->FiltroPasaBaja_CSTATE = control_Velocidad_cal->FiltroPasaBaja_A *
|
|
control_Velocidad_X.FiltroPasaBaja_CSTATE;
|
|
_rtXdot->FiltroPasaBaja_CSTATE += control_Velocidad_B.Gain_e;
|
|
}
|
|
|
|
/* Model initialize function */
|
|
void control_Velocidad_initialize(void)
|
|
{
|
|
/* Registration code */
|
|
|
|
/* initialize non-finites */
|
|
rt_InitInfAndNaN(sizeof(real_T));
|
|
|
|
{
|
|
/* Setup solver object */
|
|
rtsiSetSimTimeStepPtr(&control_Velocidad_M->solverInfo,
|
|
&control_Velocidad_M->Timing.simTimeStep);
|
|
rtsiSetTPtr(&control_Velocidad_M->solverInfo, &rtmGetTPtr
|
|
(control_Velocidad_M));
|
|
rtsiSetStepSizePtr(&control_Velocidad_M->solverInfo,
|
|
&control_Velocidad_M->Timing.stepSize0);
|
|
rtsiSetdXPtr(&control_Velocidad_M->solverInfo, &control_Velocidad_M->derivs);
|
|
rtsiSetContStatesPtr(&control_Velocidad_M->solverInfo, (real_T **)
|
|
&control_Velocidad_M->contStates);
|
|
rtsiSetNumContStatesPtr(&control_Velocidad_M->solverInfo,
|
|
&control_Velocidad_M->Sizes.numContStates);
|
|
rtsiSetNumPeriodicContStatesPtr(&control_Velocidad_M->solverInfo,
|
|
&control_Velocidad_M->Sizes.numPeriodicContStates);
|
|
rtsiSetPeriodicContStateIndicesPtr(&control_Velocidad_M->solverInfo,
|
|
&control_Velocidad_M->periodicContStateIndices);
|
|
rtsiSetPeriodicContStateRangesPtr(&control_Velocidad_M->solverInfo,
|
|
&control_Velocidad_M->periodicContStateRanges);
|
|
rtsiSetContStateDisabledPtr(&control_Velocidad_M->solverInfo, (boolean_T**)
|
|
&control_Velocidad_M->contStateDisabled);
|
|
rtsiSetErrorStatusPtr(&control_Velocidad_M->solverInfo, (&rtmGetErrorStatus
|
|
(control_Velocidad_M)));
|
|
rtsiSetRTModelPtr(&control_Velocidad_M->solverInfo, control_Velocidad_M);
|
|
}
|
|
|
|
rtsiSetSimTimeStep(&control_Velocidad_M->solverInfo, MAJOR_TIME_STEP);
|
|
rtsiSetIsMinorTimeStepWithModeChange(&control_Velocidad_M->solverInfo, false);
|
|
rtsiSetIsContModeFrozen(&control_Velocidad_M->solverInfo, false);
|
|
control_Velocidad_M->intgData.y = control_Velocidad_M->odeY;
|
|
control_Velocidad_M->intgData.f[0] = control_Velocidad_M->odeF[0];
|
|
control_Velocidad_M->intgData.f[1] = control_Velocidad_M->odeF[1];
|
|
control_Velocidad_M->intgData.f[2] = control_Velocidad_M->odeF[2];
|
|
control_Velocidad_M->contStates = ((X_control_Velocidad_T *)
|
|
&control_Velocidad_X);
|
|
control_Velocidad_M->contStateDisabled = ((XDis_control_Velocidad_T *)
|
|
&control_Velocidad_XDis);
|
|
control_Velocidad_M->Timing.tStart = (0.0);
|
|
rtsiSetSolverData(&control_Velocidad_M->solverInfo, static_cast<void *>
|
|
(&control_Velocidad_M->intgData));
|
|
rtsiSetSolverName(&control_Velocidad_M->solverInfo,"ode3");
|
|
control_Velocidad_M->solverInfoPtr = (&control_Velocidad_M->solverInfo);
|
|
|
|
/* Initialize timing info */
|
|
{
|
|
int_T *mdlTsMap = control_Velocidad_M->Timing.sampleTimeTaskIDArray;
|
|
mdlTsMap[0] = 0;
|
|
mdlTsMap[1] = 1;
|
|
control_Velocidad_M->Timing.sampleTimeTaskIDPtr = (&mdlTsMap[0]);
|
|
control_Velocidad_M->Timing.sampleTimes =
|
|
(&control_Velocidad_M->Timing.sampleTimesArray[0]);
|
|
control_Velocidad_M->Timing.offsetTimes =
|
|
(&control_Velocidad_M->Timing.offsetTimesArray[0]);
|
|
|
|
/* task periods */
|
|
control_Velocidad_M->Timing.sampleTimes[0] = (0.0);
|
|
control_Velocidad_M->Timing.sampleTimes[1] = (5.0E-5);
|
|
|
|
/* task offsets */
|
|
control_Velocidad_M->Timing.offsetTimes[0] = (0.0);
|
|
control_Velocidad_M->Timing.offsetTimes[1] = (0.0);
|
|
}
|
|
|
|
rtmSetTPtr(control_Velocidad_M, &control_Velocidad_M->Timing.tArray[0]);
|
|
|
|
{
|
|
int_T *mdlSampleHits = control_Velocidad_M->Timing.sampleHitArray;
|
|
mdlSampleHits[0] = 1;
|
|
mdlSampleHits[1] = 1;
|
|
control_Velocidad_M->Timing.sampleHits = (&mdlSampleHits[0]);
|
|
}
|
|
|
|
rtmSetTFinal(control_Velocidad_M, -1);
|
|
control_Velocidad_M->Timing.stepSize0 = 5.0E-5;
|
|
control_Velocidad_M->Timing.stepSize1 = 5.0E-5;
|
|
control_Velocidad_M->solverInfoPtr = (&control_Velocidad_M->solverInfo);
|
|
control_Velocidad_M->Timing.stepSize = (5.0E-5);
|
|
rtsiSetFixedStepSize(&control_Velocidad_M->solverInfo, 5.0E-5);
|
|
rtsiSetSolverMode(&control_Velocidad_M->solverInfo, SOLVER_MODE_SINGLETASKING);
|
|
|
|
/* block I/O */
|
|
(void) std::memset((static_cast<void *>(&control_Velocidad_B)), 0,
|
|
sizeof(B_control_Velocidad_T));
|
|
|
|
/* states (continuous) */
|
|
{
|
|
(void) std::memset(static_cast<void *>(&control_Velocidad_X), 0,
|
|
sizeof(X_control_Velocidad_T));
|
|
}
|
|
|
|
/* disabled states */
|
|
{
|
|
(void) std::memset(static_cast<void *>(&control_Velocidad_XDis), 0,
|
|
sizeof(XDis_control_Velocidad_T));
|
|
}
|
|
|
|
/* states (dwork) */
|
|
(void) std::memset(static_cast<void *>(&control_Velocidad_DW), 0,
|
|
sizeof(DW_control_Velocidad_T));
|
|
|
|
/* child S-Function registration */
|
|
{
|
|
RTWSfcnInfo *sfcnInfo = &control_Velocidad_M->NonInlinedSFcns.sfcnInfo;
|
|
control_Velocidad_M->sfcnInfo = (sfcnInfo);
|
|
rtssSetErrorStatusPtr(sfcnInfo, (&rtmGetErrorStatus(control_Velocidad_M)));
|
|
control_Velocidad_M->Sizes.numSampTimes = (2);
|
|
rtssSetNumRootSampTimesPtr(sfcnInfo,
|
|
&control_Velocidad_M->Sizes.numSampTimes);
|
|
control_Velocidad_M->NonInlinedSFcns.taskTimePtrs[0] = (&rtmGetTPtr
|
|
(control_Velocidad_M)[0]);
|
|
control_Velocidad_M->NonInlinedSFcns.taskTimePtrs[1] = (&rtmGetTPtr
|
|
(control_Velocidad_M)[1]);
|
|
rtssSetTPtrPtr(sfcnInfo,control_Velocidad_M->NonInlinedSFcns.taskTimePtrs);
|
|
rtssSetTStartPtr(sfcnInfo, &rtmGetTStart(control_Velocidad_M));
|
|
rtssSetTFinalPtr(sfcnInfo, &rtmGetTFinal(control_Velocidad_M));
|
|
rtssSetTimeOfLastOutputPtr(sfcnInfo, &rtmGetTimeOfLastOutput
|
|
(control_Velocidad_M));
|
|
rtssSetStepSizePtr(sfcnInfo, &control_Velocidad_M->Timing.stepSize);
|
|
rtssSetStopRequestedPtr(sfcnInfo, &rtmGetStopRequested(control_Velocidad_M));
|
|
rtssSetDerivCacheNeedsResetPtr(sfcnInfo,
|
|
&control_Velocidad_M->derivCacheNeedsReset);
|
|
rtssSetZCCacheNeedsResetPtr(sfcnInfo,
|
|
&control_Velocidad_M->zCCacheNeedsReset);
|
|
rtssSetContTimeOutputInconsistentWithStateAtMajorStepPtr(sfcnInfo,
|
|
&control_Velocidad_M->CTOutputIncnstWithState);
|
|
rtssSetSampleHitsPtr(sfcnInfo, &control_Velocidad_M->Timing.sampleHits);
|
|
rtssSetPerTaskSampleHitsPtr(sfcnInfo,
|
|
&control_Velocidad_M->Timing.perTaskSampleHits);
|
|
rtssSetSimModePtr(sfcnInfo, &control_Velocidad_M->simMode);
|
|
rtssSetSolverInfoPtr(sfcnInfo, &control_Velocidad_M->solverInfoPtr);
|
|
}
|
|
|
|
control_Velocidad_M->Sizes.numSFcns = (2);
|
|
|
|
/* register each child */
|
|
{
|
|
(void) std::memset(static_cast<void *>
|
|
(&control_Velocidad_M->NonInlinedSFcns.childSFunctions[0]),
|
|
0,
|
|
2*sizeof(SimStruct));
|
|
control_Velocidad_M->childSfunctions =
|
|
(&control_Velocidad_M->NonInlinedSFcns.childSFunctionPtrs[0]);
|
|
control_Velocidad_M->childSfunctions[0] =
|
|
(&control_Velocidad_M->NonInlinedSFcns.childSFunctions[0]);
|
|
control_Velocidad_M->childSfunctions[1] =
|
|
(&control_Velocidad_M->NonInlinedSFcns.childSFunctions[1]);
|
|
|
|
/* Level2 S-Function Block: control_Velocidad/<Root>/Digital output (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = control_Velocidad_M->childSfunctions[0];
|
|
|
|
/* timing info */
|
|
time_T *sfcnPeriod = control_Velocidad_M->NonInlinedSFcns.Sfcn0.sfcnPeriod;
|
|
time_T *sfcnOffset = control_Velocidad_M->NonInlinedSFcns.Sfcn0.sfcnOffset;
|
|
int_T *sfcnTsMap = control_Velocidad_M->NonInlinedSFcns.Sfcn0.sfcnTsMap;
|
|
(void) std::memset(static_cast<void*>(sfcnPeriod), 0,
|
|
sizeof(time_T)*1);
|
|
(void) std::memset(static_cast<void*>(sfcnOffset), 0,
|
|
sizeof(time_T)*1);
|
|
ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
|
|
ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
|
|
ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
|
|
|
|
{
|
|
ssSetBlkInfo2Ptr(rts, &control_Velocidad_M->NonInlinedSFcns.blkInfo2[0]);
|
|
}
|
|
|
|
_ssSetBlkInfo2PortInfo2Ptr(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.inputOutputPortInfo2[0]);
|
|
|
|
/* Set up the mdlInfo pointer */
|
|
ssSetRTWSfcnInfo(rts, control_Velocidad_M->sfcnInfo);
|
|
|
|
/* Allocate memory of model methods 2 */
|
|
{
|
|
ssSetModelMethods2(rts, &control_Velocidad_M->NonInlinedSFcns.methods2[0]);
|
|
}
|
|
|
|
/* Allocate memory of model methods 3 */
|
|
{
|
|
ssSetModelMethods3(rts, &control_Velocidad_M->NonInlinedSFcns.methods3[0]);
|
|
}
|
|
|
|
/* Allocate memory of model methods 4 */
|
|
{
|
|
ssSetModelMethods4(rts, &control_Velocidad_M->NonInlinedSFcns.methods4[0]);
|
|
}
|
|
|
|
/* Allocate memory for states auxilliary information */
|
|
{
|
|
ssSetStatesInfo2(rts, &control_Velocidad_M->NonInlinedSFcns.statesInfo2
|
|
[0]);
|
|
ssSetPeriodicStatesInfo(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.periodicStatesInfo[0]);
|
|
}
|
|
|
|
/* inputs */
|
|
{
|
|
_ssSetNumInputPorts(rts, 6);
|
|
ssSetPortInfoForInputs(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
|
|
ssSetPortInfoForInputs(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
|
|
_ssSetPortInfo2ForInputUnits(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn0.inputPortUnits[0]);
|
|
ssSetInputPortUnit(rts, 0, 0);
|
|
ssSetInputPortUnit(rts, 1, 0);
|
|
ssSetInputPortUnit(rts, 2, 0);
|
|
ssSetInputPortUnit(rts, 3, 0);
|
|
ssSetInputPortUnit(rts, 4, 0);
|
|
ssSetInputPortUnit(rts, 5, 0);
|
|
_ssSetPortInfo2ForInputCoSimAttribute(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn0.inputPortCoSimAttribute[0]);
|
|
ssSetInputPortIsContinuousQuantity(rts, 0, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 1, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 2, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 3, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 4, 0);
|
|
ssSetInputPortIsContinuousQuantity(rts, 5, 0);
|
|
|
|
/* port 0 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 0, 1);
|
|
ssSetInputPortSignal(rts, 0, &control_Velocidad_B.CastToDouble[0]);
|
|
_ssSetInputPortNumDimensions(rts, 0, 1);
|
|
ssSetInputPortWidthAsInt(rts, 0, 1);
|
|
}
|
|
|
|
/* port 1 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 1, 1);
|
|
ssSetInputPortSignal(rts, 1, &control_Velocidad_B.CastToDouble[1]);
|
|
_ssSetInputPortNumDimensions(rts, 1, 1);
|
|
ssSetInputPortWidthAsInt(rts, 1, 1);
|
|
}
|
|
|
|
/* port 2 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 2, 1);
|
|
ssSetInputPortSignal(rts, 2, &control_Velocidad_B.CastToDouble[2]);
|
|
_ssSetInputPortNumDimensions(rts, 2, 1);
|
|
ssSetInputPortWidthAsInt(rts, 2, 1);
|
|
}
|
|
|
|
/* port 3 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 3, 1);
|
|
ssSetInputPortSignal(rts, 3, &control_Velocidad_B.CastToDouble[3]);
|
|
_ssSetInputPortNumDimensions(rts, 3, 1);
|
|
ssSetInputPortWidthAsInt(rts, 3, 1);
|
|
}
|
|
|
|
/* port 4 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 4, 1);
|
|
ssSetInputPortSignal(rts, 4, &control_Velocidad_B.CastToDouble[4]);
|
|
_ssSetInputPortNumDimensions(rts, 4, 1);
|
|
ssSetInputPortWidthAsInt(rts, 4, 1);
|
|
}
|
|
|
|
/* port 5 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 5, 1);
|
|
ssSetInputPortSignal(rts, 5, &control_Velocidad_B.CastToDouble[5]);
|
|
_ssSetInputPortNumDimensions(rts, 5, 1);
|
|
ssSetInputPortWidthAsInt(rts, 5, 1);
|
|
}
|
|
}
|
|
|
|
/* path info */
|
|
ssSetModelName(rts, "Digital output");
|
|
ssSetPath(rts, "control_Velocidad/Digital output");
|
|
ssSetRTModel(rts,control_Velocidad_M);
|
|
ssSetParentSS(rts, (NULL));
|
|
ssSetRootSS(rts, rts);
|
|
ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
|
|
|
|
/* parameters */
|
|
{
|
|
mxArray **sfcnParams = (mxArray **)
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn0.params;
|
|
ssSetSFcnParamsCount(rts, 6);
|
|
ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
|
|
ssSetSFcnParam(rts, 0, (mxArray*)
|
|
control_Velocidad_cal->Digitaloutput_P1_Size);
|
|
ssSetSFcnParam(rts, 1, (mxArray*)
|
|
control_Velocidad_cal->Digitaloutput_P2_Size);
|
|
ssSetSFcnParam(rts, 2, (mxArray*)
|
|
control_Velocidad_cal->Digitaloutput_P3_Size);
|
|
ssSetSFcnParam(rts, 3, (mxArray*)
|
|
control_Velocidad_cal->Digitaloutput_P4_Size);
|
|
ssSetSFcnParam(rts, 4, (mxArray*)
|
|
control_Velocidad_cal->Digitaloutput_P5_Size);
|
|
ssSetSFcnParam(rts, 5, (mxArray*)
|
|
control_Velocidad_cal->Digitaloutput_P6_Size);
|
|
}
|
|
|
|
/* work vectors */
|
|
ssSetIWork(rts, (int_T *) &control_Velocidad_DW.Digitaloutput_IWORK);
|
|
ssSetPWork(rts, (void **) &control_Velocidad_DW.Digitaloutput_PWORK[0]);
|
|
|
|
{
|
|
struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn0.dWork;
|
|
struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn0.dWorkAux;
|
|
ssSetSFcnDWork(rts, dWorkRecord);
|
|
ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
|
|
ssSetNumDWorkAsInt(rts, 2);
|
|
|
|
/* IWORK */
|
|
ssSetDWorkWidthAsInt(rts, 0, 1);
|
|
ssSetDWorkDataType(rts, 0,SS_INTEGER);
|
|
ssSetDWorkComplexSignal(rts, 0, 0);
|
|
ssSetDWork(rts, 0, &control_Velocidad_DW.Digitaloutput_IWORK);
|
|
|
|
/* PWORK */
|
|
ssSetDWorkWidthAsInt(rts, 1, 2);
|
|
ssSetDWorkDataType(rts, 1,SS_POINTER);
|
|
ssSetDWorkComplexSignal(rts, 1, 0);
|
|
ssSetDWork(rts, 1, &control_Velocidad_DW.Digitaloutput_PWORK[0]);
|
|
}
|
|
|
|
/* registration */
|
|
sg_fpga_do_sf_a2(rts);
|
|
sfcnInitializeSizes(rts);
|
|
sfcnInitializeSampleTimes(rts);
|
|
|
|
/* adjust sample time */
|
|
ssSetSampleTime(rts, 0, 5.0E-5);
|
|
ssSetOffsetTime(rts, 0, 0.0);
|
|
sfcnTsMap[0] = 1;
|
|
|
|
/* set compiled values of dynamic vector attributes */
|
|
ssSetNumNonsampledZCsAsInt(rts, 0);
|
|
|
|
/* Update connectivity flags for each port */
|
|
_ssSetInputPortConnected(rts, 0, 1);
|
|
_ssSetInputPortConnected(rts, 1, 1);
|
|
_ssSetInputPortConnected(rts, 2, 1);
|
|
_ssSetInputPortConnected(rts, 3, 1);
|
|
_ssSetInputPortConnected(rts, 4, 1);
|
|
_ssSetInputPortConnected(rts, 5, 1);
|
|
|
|
/* Update the BufferDstPort flags for each input port */
|
|
ssSetInputPortBufferDstPort(rts, 0, -1);
|
|
ssSetInputPortBufferDstPort(rts, 1, -1);
|
|
ssSetInputPortBufferDstPort(rts, 2, -1);
|
|
ssSetInputPortBufferDstPort(rts, 3, -1);
|
|
ssSetInputPortBufferDstPort(rts, 4, -1);
|
|
ssSetInputPortBufferDstPort(rts, 5, -1);
|
|
}
|
|
|
|
/* Level2 S-Function Block: control_Velocidad/<Root>/Digital input (sg_fpga_di_sf_a2) */
|
|
{
|
|
SimStruct *rts = control_Velocidad_M->childSfunctions[1];
|
|
|
|
/* timing info */
|
|
time_T *sfcnPeriod = control_Velocidad_M->NonInlinedSFcns.Sfcn1.sfcnPeriod;
|
|
time_T *sfcnOffset = control_Velocidad_M->NonInlinedSFcns.Sfcn1.sfcnOffset;
|
|
int_T *sfcnTsMap = control_Velocidad_M->NonInlinedSFcns.Sfcn1.sfcnTsMap;
|
|
(void) std::memset(static_cast<void*>(sfcnPeriod), 0,
|
|
sizeof(time_T)*1);
|
|
(void) std::memset(static_cast<void*>(sfcnOffset), 0,
|
|
sizeof(time_T)*1);
|
|
ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
|
|
ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
|
|
ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
|
|
|
|
{
|
|
ssSetBlkInfo2Ptr(rts, &control_Velocidad_M->NonInlinedSFcns.blkInfo2[1]);
|
|
}
|
|
|
|
_ssSetBlkInfo2PortInfo2Ptr(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.inputOutputPortInfo2[1]);
|
|
|
|
/* Set up the mdlInfo pointer */
|
|
ssSetRTWSfcnInfo(rts, control_Velocidad_M->sfcnInfo);
|
|
|
|
/* Allocate memory of model methods 2 */
|
|
{
|
|
ssSetModelMethods2(rts, &control_Velocidad_M->NonInlinedSFcns.methods2[1]);
|
|
}
|
|
|
|
/* Allocate memory of model methods 3 */
|
|
{
|
|
ssSetModelMethods3(rts, &control_Velocidad_M->NonInlinedSFcns.methods3[1]);
|
|
}
|
|
|
|
/* Allocate memory of model methods 4 */
|
|
{
|
|
ssSetModelMethods4(rts, &control_Velocidad_M->NonInlinedSFcns.methods4[1]);
|
|
}
|
|
|
|
/* Allocate memory for states auxilliary information */
|
|
{
|
|
ssSetStatesInfo2(rts, &control_Velocidad_M->NonInlinedSFcns.statesInfo2
|
|
[1]);
|
|
ssSetPeriodicStatesInfo(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.periodicStatesInfo[1]);
|
|
}
|
|
|
|
/* outputs */
|
|
{
|
|
ssSetPortInfoForOutputs(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn1.outputPortInfo[0]);
|
|
ssSetPortInfoForOutputs(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn1.outputPortInfo[0]);
|
|
_ssSetNumOutputPorts(rts, 2);
|
|
_ssSetPortInfo2ForOutputUnits(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn1.outputPortUnits[0]);
|
|
ssSetOutputPortUnit(rts, 0, 0);
|
|
ssSetOutputPortUnit(rts, 1, 0);
|
|
_ssSetPortInfo2ForOutputCoSimAttribute(rts,
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn1.outputPortCoSimAttribute[0]);
|
|
ssSetOutputPortIsContinuousQuantity(rts, 0, 0);
|
|
ssSetOutputPortIsContinuousQuantity(rts, 1, 0);
|
|
|
|
/* port 0 */
|
|
{
|
|
_ssSetOutputPortNumDimensions(rts, 0, 1);
|
|
ssSetOutputPortWidthAsInt(rts, 0, 1);
|
|
ssSetOutputPortSignal(rts, 0, ((real_T *)
|
|
&control_Velocidad_B.Digitalinput_o1));
|
|
}
|
|
|
|
/* port 1 */
|
|
{
|
|
_ssSetOutputPortNumDimensions(rts, 1, 1);
|
|
ssSetOutputPortWidthAsInt(rts, 1, 1);
|
|
ssSetOutputPortSignal(rts, 1, ((real_T *)
|
|
&control_Velocidad_B.Digitalinput_o2));
|
|
}
|
|
}
|
|
|
|
/* path info */
|
|
ssSetModelName(rts, "Digital input");
|
|
ssSetPath(rts, "control_Velocidad/Digital input");
|
|
ssSetRTModel(rts,control_Velocidad_M);
|
|
ssSetParentSS(rts, (NULL));
|
|
ssSetRootSS(rts, rts);
|
|
ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
|
|
|
|
/* parameters */
|
|
{
|
|
mxArray **sfcnParams = (mxArray **)
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn1.params;
|
|
ssSetSFcnParamsCount(rts, 4);
|
|
ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
|
|
ssSetSFcnParam(rts, 0, (mxArray*)
|
|
control_Velocidad_cal->Digitalinput_P1_Size);
|
|
ssSetSFcnParam(rts, 1, (mxArray*)
|
|
control_Velocidad_cal->Digitalinput_P2_Size);
|
|
ssSetSFcnParam(rts, 2, (mxArray*)
|
|
control_Velocidad_cal->Digitalinput_P3_Size);
|
|
ssSetSFcnParam(rts, 3, (mxArray*)
|
|
control_Velocidad_cal->Digitalinput_P4_Size);
|
|
}
|
|
|
|
/* work vectors */
|
|
ssSetPWork(rts, (void **) &control_Velocidad_DW.Digitalinput_PWORK[0]);
|
|
|
|
{
|
|
struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn1.dWork;
|
|
struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
|
|
&control_Velocidad_M->NonInlinedSFcns.Sfcn1.dWorkAux;
|
|
ssSetSFcnDWork(rts, dWorkRecord);
|
|
ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
|
|
ssSetNumDWorkAsInt(rts, 1);
|
|
|
|
/* PWORK */
|
|
ssSetDWorkWidthAsInt(rts, 0, 2);
|
|
ssSetDWorkDataType(rts, 0,SS_POINTER);
|
|
ssSetDWorkComplexSignal(rts, 0, 0);
|
|
ssSetDWork(rts, 0, &control_Velocidad_DW.Digitalinput_PWORK[0]);
|
|
}
|
|
|
|
/* registration */
|
|
sg_fpga_di_sf_a2(rts);
|
|
sfcnInitializeSizes(rts);
|
|
sfcnInitializeSampleTimes(rts);
|
|
|
|
/* adjust sample time */
|
|
ssSetSampleTime(rts, 0, 5.0E-5);
|
|
ssSetOffsetTime(rts, 0, 0.0);
|
|
sfcnTsMap[0] = 1;
|
|
|
|
/* set compiled values of dynamic vector attributes */
|
|
ssSetNumNonsampledZCsAsInt(rts, 0);
|
|
|
|
/* Update connectivity flags for each port */
|
|
_ssSetOutputPortConnected(rts, 0, 1);
|
|
_ssSetOutputPortConnected(rts, 1, 1);
|
|
_ssSetOutputPortBeingMerged(rts, 0, 0);
|
|
_ssSetOutputPortBeingMerged(rts, 1, 0);
|
|
|
|
/* Update the BufferDstPort flags for each input port */
|
|
}
|
|
}
|
|
|
|
/* Start for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
|
|
/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = control_Velocidad_M->childSfunctions[0];
|
|
sfcnStart(rts);
|
|
if (ssGetErrorStatus(rts) != (NULL))
|
|
return;
|
|
}
|
|
|
|
/* Start for S-Function (sg_fpga_di_sf_a2): '<Root>/Digital input' */
|
|
/* Level2 S-Function Block: '<Root>/Digital input' (sg_fpga_di_sf_a2) */
|
|
{
|
|
SimStruct *rts = control_Velocidad_M->childSfunctions[1];
|
|
sfcnStart(rts);
|
|
if (ssGetErrorStatus(rts) != (NULL))
|
|
return;
|
|
}
|
|
|
|
control_Velocidad_PrevZCX.TriggeredSubsystem_Trig_ZCE = POS_ZCSIG;
|
|
|
|
{
|
|
int32_T i;
|
|
|
|
/* InitializeConditions for DiscreteIntegrator: '<S2>/Discrete-Time Integrator' */
|
|
control_Velocidad_DW.DiscreteTimeIntegrator_DSTATE =
|
|
control_Velocidad_cal->DiscreteTimeIntegrator_IC;
|
|
|
|
/* InitializeConditions for Memory: '<S5>/Memory' */
|
|
control_Velocidad_DW.Memory_PreviousInput =
|
|
control_Velocidad_cal->EdgeDetector_ic;
|
|
|
|
/* InitializeConditions for Delay: '<S1>/Delay4' */
|
|
control_Velocidad_DW.Delay4_DSTATE =
|
|
control_Velocidad_cal->Delay4_InitialCondition;
|
|
|
|
/* InitializeConditions for Delay: '<S1>/Delay1' */
|
|
control_Velocidad_DW.Delay1_DSTATE =
|
|
control_Velocidad_cal->Delay1_InitialCondition;
|
|
|
|
/* InitializeConditions for TransferFcn: '<S1>/Filtro Pasa Baja' */
|
|
control_Velocidad_X.FiltroPasaBaja_CSTATE = 0.0;
|
|
for (i = 0; i < 100; i++) {
|
|
/* InitializeConditions for Delay: '<S1>/Delay3' */
|
|
control_Velocidad_DW.Delay3_DSTATE[i] =
|
|
control_Velocidad_cal->Delay3_InitialCondition;
|
|
|
|
/* InitializeConditions for Delay: '<S1>/Delay' */
|
|
control_Velocidad_DW.Delay_DSTATE[i] =
|
|
control_Velocidad_cal->Delay_InitialCondition;
|
|
}
|
|
|
|
/* SystemInitialize for Enabled SubSystem: '<S5>/POSITIVE Edge' */
|
|
/* SystemInitialize for RelationalOperator: '<S8>/Relational Operator1' incorporates:
|
|
* Outport: '<S8>/OUT'
|
|
*/
|
|
control_Velocidad_B.RelationalOperator1 = control_Velocidad_cal->OUT_Y0_p;
|
|
|
|
/* End of SystemInitialize for SubSystem: '<S5>/POSITIVE Edge' */
|
|
|
|
/* SystemInitialize for Enabled SubSystem: '<S5>/NEGATIVE Edge' */
|
|
/* SystemInitialize for RelationalOperator: '<S7>/Relational Operator1' incorporates:
|
|
* Outport: '<S7>/OUT'
|
|
*/
|
|
control_Velocidad_B.RelationalOperator1_e = control_Velocidad_cal->OUT_Y0;
|
|
|
|
/* End of SystemInitialize for SubSystem: '<S5>/NEGATIVE Edge' */
|
|
|
|
/* SystemInitialize for Triggered SubSystem: '<S6>/Triggered Subsystem' */
|
|
/* SystemInitialize for SignalConversion generated from: '<S9>/In1' incorporates:
|
|
* Outport: '<S9>/Out1'
|
|
*/
|
|
control_Velocidad_B.In1 = control_Velocidad_cal->Out1_Y0;
|
|
|
|
/* End of SystemInitialize for SubSystem: '<S6>/Triggered Subsystem' */
|
|
}
|
|
}
|
|
|
|
/* Model terminate function */
|
|
void control_Velocidad_terminate(void)
|
|
{
|
|
/* Terminate for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
|
|
/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = control_Velocidad_M->childSfunctions[0];
|
|
sfcnTerminate(rts);
|
|
}
|
|
|
|
/* Terminate for S-Function (sg_fpga_di_sf_a2): '<Root>/Digital input' */
|
|
/* Level2 S-Function Block: '<Root>/Digital input' (sg_fpga_di_sf_a2) */
|
|
{
|
|
SimStruct *rts = control_Velocidad_M->childSfunctions[1];
|
|
sfcnTerminate(rts);
|
|
}
|
|
|
|
/* user code (Terminate function Trailer) */
|
|
{
|
|
freeFPGAModuleSgLib((uint32_t)1);
|
|
}
|
|
}
|