548 lines
19 KiB
C++
548 lines
19 KiB
C++
/*
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* ArranqueVF.cpp
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*
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* Academic License - for use in teaching, academic research, and meeting
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* course requirements at degree granting institutions only. Not for
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* government, commercial, or other organizational use.
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*
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* Code generation for model "ArranqueVF".
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*
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* Model version : 1.13
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* Simulink Coder version : 24.2 (R2024b) 21-Jun-2024
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* C++ source code generated on : Tue Jun 3 11:16:51 2025
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*
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* Target selection: speedgoat.tlc
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* Note: GRT includes extra infrastructure and instrumentation for prototyping
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* Embedded hardware selection: Intel->x86-64 (Linux 64)
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* Code generation objectives: Unspecified
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* Validation result: Not run
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*/
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#include "ArranqueVF.h"
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#include "ArranqueVF_cal.h"
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#include "rtwtypes.h"
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#include "ArranqueVF_private.h"
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#include <cstring>
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extern "C"
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{
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#include "rt_nonfinite.h"
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}
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const real_T ArranqueVF_RGND = 0.0; /* real_T ground */
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/* Block signals (default storage) */
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B_ArranqueVF_T ArranqueVF_B;
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/* Block states (default storage) */
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DW_ArranqueVF_T ArranqueVF_DW;
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/* Real-time model */
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RT_MODEL_ArranqueVF_T ArranqueVF_M_ = RT_MODEL_ArranqueVF_T();
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RT_MODEL_ArranqueVF_T *const ArranqueVF_M = &ArranqueVF_M_;
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/* Model step function */
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void ArranqueVF_step(void)
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{
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/* Constant: '<Root>/Constant' */
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ArranqueVF_B.Constant = ArranqueVF_cal->Constant_Value;
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/* S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output1' */
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/* Level2 S-Function Block: '<Root>/Digital output1' (sg_fpga_do_sf_a2) */
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{
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SimStruct *rts = ArranqueVF_M->childSfunctions[0];
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sfcnOutputs(rts,0);
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}
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/* S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
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/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
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{
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SimStruct *rts = ArranqueVF_M->childSfunctions[1];
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sfcnOutputs(rts,0);
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}
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/* user code (Output function Trailer) */
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{
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}
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/* Update absolute time for base rate */
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/* The "clockTick0" counts the number of times the code of this task has
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* been executed. The absolute time is the multiplication of "clockTick0"
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* and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
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* overflow during the application lifespan selected.
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* Timer of this task consists of two 32 bit unsigned integers.
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* The two integers represent the low bits Timing.clockTick0 and the high bits
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* Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
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*/
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if (!(++ArranqueVF_M->Timing.clockTick0)) {
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++ArranqueVF_M->Timing.clockTickH0;
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}
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ArranqueVF_M->Timing.t[0] = ArranqueVF_M->Timing.clockTick0 *
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ArranqueVF_M->Timing.stepSize0 + ArranqueVF_M->Timing.clockTickH0 *
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ArranqueVF_M->Timing.stepSize0 * 4294967296.0;
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}
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/* Model initialize function */
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void ArranqueVF_initialize(void)
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{
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/* Registration code */
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/* initialize non-finites */
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rt_InitInfAndNaN(sizeof(real_T));
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rtsiSetSolverName(&ArranqueVF_M->solverInfo,"FixedStepDiscrete");
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ArranqueVF_M->solverInfoPtr = (&ArranqueVF_M->solverInfo);
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/* Initialize timing info */
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{
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int_T *mdlTsMap = ArranqueVF_M->Timing.sampleTimeTaskIDArray;
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mdlTsMap[0] = 0;
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ArranqueVF_M->Timing.sampleTimeTaskIDPtr = (&mdlTsMap[0]);
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ArranqueVF_M->Timing.sampleTimes = (&ArranqueVF_M->Timing.sampleTimesArray[0]);
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ArranqueVF_M->Timing.offsetTimes = (&ArranqueVF_M->Timing.offsetTimesArray[0]);
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/* task periods */
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ArranqueVF_M->Timing.sampleTimes[0] = (0.0001);
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/* task offsets */
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ArranqueVF_M->Timing.offsetTimes[0] = (0.0);
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}
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rtmSetTPtr(ArranqueVF_M, &ArranqueVF_M->Timing.tArray[0]);
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{
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int_T *mdlSampleHits = ArranqueVF_M->Timing.sampleHitArray;
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mdlSampleHits[0] = 1;
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ArranqueVF_M->Timing.sampleHits = (&mdlSampleHits[0]);
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}
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rtmSetTFinal(ArranqueVF_M, -1);
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ArranqueVF_M->Timing.stepSize0 = 0.0001;
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ArranqueVF_M->solverInfoPtr = (&ArranqueVF_M->solverInfo);
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ArranqueVF_M->Timing.stepSize = (0.0001);
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rtsiSetFixedStepSize(&ArranqueVF_M->solverInfo, 0.0001);
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rtsiSetSolverMode(&ArranqueVF_M->solverInfo, SOLVER_MODE_SINGLETASKING);
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/* block I/O */
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(void) std::memset((static_cast<void *>(&ArranqueVF_B)), 0,
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sizeof(B_ArranqueVF_T));
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/* states (dwork) */
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(void) std::memset(static_cast<void *>(&ArranqueVF_DW), 0,
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sizeof(DW_ArranqueVF_T));
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/* child S-Function registration */
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{
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RTWSfcnInfo *sfcnInfo = &ArranqueVF_M->NonInlinedSFcns.sfcnInfo;
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ArranqueVF_M->sfcnInfo = (sfcnInfo);
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rtssSetErrorStatusPtr(sfcnInfo, (&rtmGetErrorStatus(ArranqueVF_M)));
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ArranqueVF_M->Sizes.numSampTimes = (1);
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rtssSetNumRootSampTimesPtr(sfcnInfo, &ArranqueVF_M->Sizes.numSampTimes);
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ArranqueVF_M->NonInlinedSFcns.taskTimePtrs[0] = (&rtmGetTPtr(ArranqueVF_M)[0]);
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rtssSetTPtrPtr(sfcnInfo,ArranqueVF_M->NonInlinedSFcns.taskTimePtrs);
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rtssSetTStartPtr(sfcnInfo, &rtmGetTStart(ArranqueVF_M));
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rtssSetTFinalPtr(sfcnInfo, &rtmGetTFinal(ArranqueVF_M));
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rtssSetTimeOfLastOutputPtr(sfcnInfo, &rtmGetTimeOfLastOutput(ArranqueVF_M));
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rtssSetStepSizePtr(sfcnInfo, &ArranqueVF_M->Timing.stepSize);
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rtssSetStopRequestedPtr(sfcnInfo, &rtmGetStopRequested(ArranqueVF_M));
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rtssSetDerivCacheNeedsResetPtr(sfcnInfo, &ArranqueVF_M->derivCacheNeedsReset);
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rtssSetZCCacheNeedsResetPtr(sfcnInfo, &ArranqueVF_M->zCCacheNeedsReset);
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rtssSetContTimeOutputInconsistentWithStateAtMajorStepPtr(sfcnInfo,
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&ArranqueVF_M->CTOutputIncnstWithState);
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rtssSetSampleHitsPtr(sfcnInfo, &ArranqueVF_M->Timing.sampleHits);
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rtssSetPerTaskSampleHitsPtr(sfcnInfo,
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&ArranqueVF_M->Timing.perTaskSampleHits);
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rtssSetSimModePtr(sfcnInfo, &ArranqueVF_M->simMode);
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rtssSetSolverInfoPtr(sfcnInfo, &ArranqueVF_M->solverInfoPtr);
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}
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ArranqueVF_M->Sizes.numSFcns = (2);
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/* register each child */
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{
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(void) std::memset(static_cast<void *>
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(&ArranqueVF_M->NonInlinedSFcns.childSFunctions[0]), 0,
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2*sizeof(SimStruct));
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ArranqueVF_M->childSfunctions =
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(&ArranqueVF_M->NonInlinedSFcns.childSFunctionPtrs[0]);
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ArranqueVF_M->childSfunctions[0] =
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(&ArranqueVF_M->NonInlinedSFcns.childSFunctions[0]);
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ArranqueVF_M->childSfunctions[1] =
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(&ArranqueVF_M->NonInlinedSFcns.childSFunctions[1]);
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/* Level2 S-Function Block: ArranqueVF/<Root>/Digital output1 (sg_fpga_do_sf_a2) */
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{
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SimStruct *rts = ArranqueVF_M->childSfunctions[0];
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/* timing info */
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time_T *sfcnPeriod = ArranqueVF_M->NonInlinedSFcns.Sfcn0.sfcnPeriod;
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time_T *sfcnOffset = ArranqueVF_M->NonInlinedSFcns.Sfcn0.sfcnOffset;
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int_T *sfcnTsMap = ArranqueVF_M->NonInlinedSFcns.Sfcn0.sfcnTsMap;
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(void) std::memset(static_cast<void*>(sfcnPeriod), 0,
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sizeof(time_T)*1);
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(void) std::memset(static_cast<void*>(sfcnOffset), 0,
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sizeof(time_T)*1);
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ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
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ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
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ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
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{
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ssSetBlkInfo2Ptr(rts, &ArranqueVF_M->NonInlinedSFcns.blkInfo2[0]);
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}
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_ssSetBlkInfo2PortInfo2Ptr(rts,
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&ArranqueVF_M->NonInlinedSFcns.inputOutputPortInfo2[0]);
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/* Set up the mdlInfo pointer */
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ssSetRTWSfcnInfo(rts, ArranqueVF_M->sfcnInfo);
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/* Allocate memory of model methods 2 */
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{
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ssSetModelMethods2(rts, &ArranqueVF_M->NonInlinedSFcns.methods2[0]);
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}
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/* Allocate memory of model methods 3 */
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{
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ssSetModelMethods3(rts, &ArranqueVF_M->NonInlinedSFcns.methods3[0]);
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}
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/* Allocate memory of model methods 4 */
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{
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ssSetModelMethods4(rts, &ArranqueVF_M->NonInlinedSFcns.methods4[0]);
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}
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/* Allocate memory for states auxilliary information */
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{
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ssSetStatesInfo2(rts, &ArranqueVF_M->NonInlinedSFcns.statesInfo2[0]);
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ssSetPeriodicStatesInfo(rts,
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&ArranqueVF_M->NonInlinedSFcns.periodicStatesInfo[0]);
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}
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/* inputs */
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{
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_ssSetNumInputPorts(rts, 3);
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ssSetPortInfoForInputs(rts,
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&ArranqueVF_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
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ssSetPortInfoForInputs(rts,
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&ArranqueVF_M->NonInlinedSFcns.Sfcn0.inputPortInfo[0]);
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_ssSetPortInfo2ForInputUnits(rts,
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&ArranqueVF_M->NonInlinedSFcns.Sfcn0.inputPortUnits[0]);
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ssSetInputPortUnit(rts, 0, 0);
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ssSetInputPortUnit(rts, 1, 0);
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ssSetInputPortUnit(rts, 2, 0);
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_ssSetPortInfo2ForInputCoSimAttribute(rts,
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&ArranqueVF_M->NonInlinedSFcns.Sfcn0.inputPortCoSimAttribute[0]);
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ssSetInputPortIsContinuousQuantity(rts, 0, 0);
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ssSetInputPortIsContinuousQuantity(rts, 1, 0);
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ssSetInputPortIsContinuousQuantity(rts, 2, 0);
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/* port 0 */
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{
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ssSetInputPortRequiredContiguous(rts, 0, 1);
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ssSetInputPortSignal(rts, 0, (const_cast<real_T*>(&ArranqueVF_RGND)));
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_ssSetInputPortNumDimensions(rts, 0, 1);
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ssSetInputPortWidthAsInt(rts, 0, 1);
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}
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/* port 1 */
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{
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ssSetInputPortRequiredContiguous(rts, 1, 1);
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ssSetInputPortSignal(rts, 1, (const_cast<real_T*>(&ArranqueVF_RGND)));
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_ssSetInputPortNumDimensions(rts, 1, 1);
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ssSetInputPortWidthAsInt(rts, 1, 1);
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}
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/* port 2 */
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{
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ssSetInputPortRequiredContiguous(rts, 2, 1);
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ssSetInputPortSignal(rts, 2, &ArranqueVF_B.Constant);
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_ssSetInputPortNumDimensions(rts, 2, 1);
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ssSetInputPortWidthAsInt(rts, 2, 1);
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}
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}
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/* path info */
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ssSetModelName(rts, "Digital output1");
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ssSetPath(rts, "ArranqueVF/Digital output1");
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ssSetRTModel(rts,ArranqueVF_M);
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ssSetParentSS(rts, (NULL));
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ssSetRootSS(rts, rts);
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ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
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/* parameters */
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{
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mxArray **sfcnParams = (mxArray **)
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&ArranqueVF_M->NonInlinedSFcns.Sfcn0.params;
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ssSetSFcnParamsCount(rts, 6);
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ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
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ssSetSFcnParam(rts, 0, (mxArray*)ArranqueVF_cal->Digitaloutput1_P1_Size);
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ssSetSFcnParam(rts, 1, (mxArray*)ArranqueVF_cal->Digitaloutput1_P2_Size);
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ssSetSFcnParam(rts, 2, (mxArray*)ArranqueVF_cal->Digitaloutput1_P3_Size);
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ssSetSFcnParam(rts, 3, (mxArray*)ArranqueVF_cal->Digitaloutput1_P4_Size);
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ssSetSFcnParam(rts, 4, (mxArray*)ArranqueVF_cal->Digitaloutput1_P5_Size);
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ssSetSFcnParam(rts, 5, (mxArray*)ArranqueVF_cal->Digitaloutput1_P6_Size);
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}
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/* work vectors */
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ssSetIWork(rts, (int_T *) &ArranqueVF_DW.Digitaloutput1_IWORK);
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ssSetPWork(rts, (void **) &ArranqueVF_DW.Digitaloutput1_PWORK[0]);
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{
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struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
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&ArranqueVF_M->NonInlinedSFcns.Sfcn0.dWork;
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struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
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&ArranqueVF_M->NonInlinedSFcns.Sfcn0.dWorkAux;
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ssSetSFcnDWork(rts, dWorkRecord);
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ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
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ssSetNumDWorkAsInt(rts, 2);
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/* IWORK */
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ssSetDWorkWidthAsInt(rts, 0, 1);
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ssSetDWorkDataType(rts, 0,SS_INTEGER);
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ssSetDWorkComplexSignal(rts, 0, 0);
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ssSetDWork(rts, 0, &ArranqueVF_DW.Digitaloutput1_IWORK);
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/* PWORK */
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ssSetDWorkWidthAsInt(rts, 1, 2);
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ssSetDWorkDataType(rts, 1,SS_POINTER);
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ssSetDWorkComplexSignal(rts, 1, 0);
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ssSetDWork(rts, 1, &ArranqueVF_DW.Digitaloutput1_PWORK[0]);
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}
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/* registration */
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sg_fpga_do_sf_a2(rts);
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sfcnInitializeSizes(rts);
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sfcnInitializeSampleTimes(rts);
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/* adjust sample time */
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ssSetSampleTime(rts, 0, 0.0001);
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ssSetOffsetTime(rts, 0, 0.0);
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sfcnTsMap[0] = 0;
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/* set compiled values of dynamic vector attributes */
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ssSetNumNonsampledZCsAsInt(rts, 0);
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/* Update connectivity flags for each port */
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_ssSetInputPortConnected(rts, 0, 0);
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_ssSetInputPortConnected(rts, 1, 0);
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_ssSetInputPortConnected(rts, 2, 1);
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/* Update the BufferDstPort flags for each input port */
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ssSetInputPortBufferDstPort(rts, 0, -1);
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ssSetInputPortBufferDstPort(rts, 1, -1);
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ssSetInputPortBufferDstPort(rts, 2, -1);
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}
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/* Level2 S-Function Block: ArranqueVF/<Root>/Digital output (sg_fpga_do_sf_a2) */
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{
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SimStruct *rts = ArranqueVF_M->childSfunctions[1];
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/* timing info */
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time_T *sfcnPeriod = ArranqueVF_M->NonInlinedSFcns.Sfcn1.sfcnPeriod;
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time_T *sfcnOffset = ArranqueVF_M->NonInlinedSFcns.Sfcn1.sfcnOffset;
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int_T *sfcnTsMap = ArranqueVF_M->NonInlinedSFcns.Sfcn1.sfcnTsMap;
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(void) std::memset(static_cast<void*>(sfcnPeriod), 0,
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sizeof(time_T)*1);
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(void) std::memset(static_cast<void*>(sfcnOffset), 0,
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sizeof(time_T)*1);
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ssSetSampleTimePtr(rts, &sfcnPeriod[0]);
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ssSetOffsetTimePtr(rts, &sfcnOffset[0]);
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ssSetSampleTimeTaskIDPtr(rts, sfcnTsMap);
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{
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ssSetBlkInfo2Ptr(rts, &ArranqueVF_M->NonInlinedSFcns.blkInfo2[1]);
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}
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_ssSetBlkInfo2PortInfo2Ptr(rts,
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&ArranqueVF_M->NonInlinedSFcns.inputOutputPortInfo2[1]);
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/* Set up the mdlInfo pointer */
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ssSetRTWSfcnInfo(rts, ArranqueVF_M->sfcnInfo);
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/* Allocate memory of model methods 2 */
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{
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ssSetModelMethods2(rts, &ArranqueVF_M->NonInlinedSFcns.methods2[1]);
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}
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/* Allocate memory of model methods 3 */
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{
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ssSetModelMethods3(rts, &ArranqueVF_M->NonInlinedSFcns.methods3[1]);
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}
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/* Allocate memory of model methods 4 */
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{
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ssSetModelMethods4(rts, &ArranqueVF_M->NonInlinedSFcns.methods4[1]);
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}
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/* Allocate memory for states auxilliary information */
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{
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ssSetStatesInfo2(rts, &ArranqueVF_M->NonInlinedSFcns.statesInfo2[1]);
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ssSetPeriodicStatesInfo(rts,
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&ArranqueVF_M->NonInlinedSFcns.periodicStatesInfo[1]);
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}
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/* inputs */
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{
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_ssSetNumInputPorts(rts, 3);
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ssSetPortInfoForInputs(rts,
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&ArranqueVF_M->NonInlinedSFcns.Sfcn1.inputPortInfo[0]);
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ssSetPortInfoForInputs(rts,
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&ArranqueVF_M->NonInlinedSFcns.Sfcn1.inputPortInfo[0]);
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_ssSetPortInfo2ForInputUnits(rts,
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&ArranqueVF_M->NonInlinedSFcns.Sfcn1.inputPortUnits[0]);
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ssSetInputPortUnit(rts, 0, 0);
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ssSetInputPortUnit(rts, 1, 0);
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ssSetInputPortUnit(rts, 2, 0);
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_ssSetPortInfo2ForInputCoSimAttribute(rts,
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&ArranqueVF_M->NonInlinedSFcns.Sfcn1.inputPortCoSimAttribute[0]);
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ssSetInputPortIsContinuousQuantity(rts, 0, 0);
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ssSetInputPortIsContinuousQuantity(rts, 1, 0);
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ssSetInputPortIsContinuousQuantity(rts, 2, 0);
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/* port 0 */
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{
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ssSetInputPortRequiredContiguous(rts, 0, 1);
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ssSetInputPortSignal(rts, 0, (const_cast<real_T*>(&ArranqueVF_RGND)));
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_ssSetInputPortNumDimensions(rts, 0, 1);
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ssSetInputPortWidthAsInt(rts, 0, 1);
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}
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/* port 1 */
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{
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ssSetInputPortRequiredContiguous(rts, 1, 1);
|
|
ssSetInputPortSignal(rts, 1, (const_cast<real_T*>(&ArranqueVF_RGND)));
|
|
_ssSetInputPortNumDimensions(rts, 1, 1);
|
|
ssSetInputPortWidthAsInt(rts, 1, 1);
|
|
}
|
|
|
|
/* port 2 */
|
|
{
|
|
ssSetInputPortRequiredContiguous(rts, 2, 1);
|
|
ssSetInputPortSignal(rts, 2, (const_cast<real_T*>(&ArranqueVF_RGND)));
|
|
_ssSetInputPortNumDimensions(rts, 2, 1);
|
|
ssSetInputPortWidthAsInt(rts, 2, 1);
|
|
}
|
|
}
|
|
|
|
/* path info */
|
|
ssSetModelName(rts, "Digital output");
|
|
ssSetPath(rts, "ArranqueVF/Digital output");
|
|
ssSetRTModel(rts,ArranqueVF_M);
|
|
ssSetParentSS(rts, (NULL));
|
|
ssSetRootSS(rts, rts);
|
|
ssSetVersion(rts, SIMSTRUCT_VERSION_LEVEL2);
|
|
|
|
/* parameters */
|
|
{
|
|
mxArray **sfcnParams = (mxArray **)
|
|
&ArranqueVF_M->NonInlinedSFcns.Sfcn1.params;
|
|
ssSetSFcnParamsCount(rts, 6);
|
|
ssSetSFcnParamsPtr(rts, &sfcnParams[0]);
|
|
ssSetSFcnParam(rts, 0, (mxArray*)ArranqueVF_cal->Digitaloutput_P1_Size);
|
|
ssSetSFcnParam(rts, 1, (mxArray*)ArranqueVF_cal->Digitaloutput_P2_Size);
|
|
ssSetSFcnParam(rts, 2, (mxArray*)ArranqueVF_cal->Digitaloutput_P3_Size);
|
|
ssSetSFcnParam(rts, 3, (mxArray*)ArranqueVF_cal->Digitaloutput_P4_Size);
|
|
ssSetSFcnParam(rts, 4, (mxArray*)ArranqueVF_cal->Digitaloutput_P5_Size);
|
|
ssSetSFcnParam(rts, 5, (mxArray*)ArranqueVF_cal->Digitaloutput_P6_Size);
|
|
}
|
|
|
|
/* work vectors */
|
|
ssSetIWork(rts, (int_T *) &ArranqueVF_DW.Digitaloutput_IWORK);
|
|
ssSetPWork(rts, (void **) &ArranqueVF_DW.Digitaloutput_PWORK[0]);
|
|
|
|
{
|
|
struct _ssDWorkRecord *dWorkRecord = (struct _ssDWorkRecord *)
|
|
&ArranqueVF_M->NonInlinedSFcns.Sfcn1.dWork;
|
|
struct _ssDWorkAuxRecord *dWorkAuxRecord = (struct _ssDWorkAuxRecord *)
|
|
&ArranqueVF_M->NonInlinedSFcns.Sfcn1.dWorkAux;
|
|
ssSetSFcnDWork(rts, dWorkRecord);
|
|
ssSetSFcnDWorkAux(rts, dWorkAuxRecord);
|
|
ssSetNumDWorkAsInt(rts, 2);
|
|
|
|
/* IWORK */
|
|
ssSetDWorkWidthAsInt(rts, 0, 1);
|
|
ssSetDWorkDataType(rts, 0,SS_INTEGER);
|
|
ssSetDWorkComplexSignal(rts, 0, 0);
|
|
ssSetDWork(rts, 0, &ArranqueVF_DW.Digitaloutput_IWORK);
|
|
|
|
/* PWORK */
|
|
ssSetDWorkWidthAsInt(rts, 1, 2);
|
|
ssSetDWorkDataType(rts, 1,SS_POINTER);
|
|
ssSetDWorkComplexSignal(rts, 1, 0);
|
|
ssSetDWork(rts, 1, &ArranqueVF_DW.Digitaloutput_PWORK[0]);
|
|
}
|
|
|
|
/* registration */
|
|
sg_fpga_do_sf_a2(rts);
|
|
sfcnInitializeSizes(rts);
|
|
sfcnInitializeSampleTimes(rts);
|
|
|
|
/* adjust sample time */
|
|
ssSetSampleTime(rts, 0, 0.0001);
|
|
ssSetOffsetTime(rts, 0, 0.0);
|
|
sfcnTsMap[0] = 0;
|
|
|
|
/* set compiled values of dynamic vector attributes */
|
|
ssSetNumNonsampledZCsAsInt(rts, 0);
|
|
|
|
/* Update connectivity flags for each port */
|
|
_ssSetInputPortConnected(rts, 0, 0);
|
|
_ssSetInputPortConnected(rts, 1, 0);
|
|
_ssSetInputPortConnected(rts, 2, 0);
|
|
|
|
/* Update the BufferDstPort flags for each input port */
|
|
ssSetInputPortBufferDstPort(rts, 0, -1);
|
|
ssSetInputPortBufferDstPort(rts, 1, -1);
|
|
ssSetInputPortBufferDstPort(rts, 2, -1);
|
|
}
|
|
}
|
|
|
|
/* Start for Constant: '<Root>/Constant' */
|
|
ArranqueVF_B.Constant = ArranqueVF_cal->Constant_Value;
|
|
|
|
/* Start for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output1' */
|
|
/* Level2 S-Function Block: '<Root>/Digital output1' (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = ArranqueVF_M->childSfunctions[0];
|
|
sfcnStart(rts);
|
|
if (ssGetErrorStatus(rts) != (NULL))
|
|
return;
|
|
}
|
|
|
|
/* Start for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
|
|
/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = ArranqueVF_M->childSfunctions[1];
|
|
sfcnStart(rts);
|
|
if (ssGetErrorStatus(rts) != (NULL))
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Model terminate function */
|
|
void ArranqueVF_terminate(void)
|
|
{
|
|
/* Terminate for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output1' */
|
|
/* Level2 S-Function Block: '<Root>/Digital output1' (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = ArranqueVF_M->childSfunctions[0];
|
|
sfcnTerminate(rts);
|
|
}
|
|
|
|
/* Terminate for S-Function (sg_fpga_do_sf_a2): '<Root>/Digital output' */
|
|
/* Level2 S-Function Block: '<Root>/Digital output' (sg_fpga_do_sf_a2) */
|
|
{
|
|
SimStruct *rts = ArranqueVF_M->childSfunctions[1];
|
|
sfcnTerminate(rts);
|
|
}
|
|
|
|
/* user code (Terminate function Trailer) */
|
|
{
|
|
freeFPGAModuleSgLib((uint32_t)1);
|
|
}
|
|
}
|