265 lines
9.8 KiB
C++
265 lines
9.8 KiB
C++
#include "VFControl.h"
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#include "VFControl_private.h"
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#include "sg_printf.h"
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#include "sg_early_init.h"
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#include "simstruc.h" // This is required if there are no S-function blocks in the model
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static RTWSfcnInfo sgEarlyInitSfcnInfo;
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struct _ssBlkInfo2 sgEarlyInitBlkInfo2 = {.rtwSfcnInfo = &sgEarlyInitSfcnInfo};
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void sg_init_sfcns(void)
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{
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sg_printf(sg_debug, "Initializing [EARLY INIT] S-functions\n");
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rtssSetErrorStatusPtr(&sgEarlyInitSfcnInfo, (&rtmGetErrorStatus(VFControl_M)));
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sg_early_init_set_blkInfo2((void*)&sgEarlyInitBlkInfo2);
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{
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uint16_t moduleArchitecture;
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int32_t ErrCode;
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uint32_t i;
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uint32_t *bitstream = NULL;
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uint8_t *fpgacode = NULL;
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char *devname;
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sg_fpga_io3xxModuleIdT moduleId;
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FILE *mcs;
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static char mcsBinFile[200];
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static char msg[500];
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sg_initModelRun();
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// Determine path to bitstream file
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if (sg_getModelBaseDir(mcsBinFile, sizeof(mcsBinFile))) {
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sprintf(msg, "Could not determine location of the model on the target machine.");
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rtmSetErrorStatus(VFControl_M, msg);
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return;
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}
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if ((strlen(mcsBinFile) + strlen("/fpga/speedgoat_IO397_RCP.mcs") + 1) > sizeof(mcsBinFile)) {
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sprintf(msg, "Path to the bitstream (model name + bitstream name) is too long.");
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rtmSetErrorStatus(VFControl_M, msg);
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return;
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}
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strcat(mcsBinFile, "/fpga/speedgoat_IO397_RCP.mcs");
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SG_PRINTF(DEBUG, "Bitstream: %s\n", mcsBinFile);
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// Read bitstream file
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if ((mcs = fopen(mcsBinFile, "r")) == NULL){
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sprintf(msg, "Bitstream file not found at %s\n", mcsBinFile);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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}
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bitstream = (uint32_t *) malloc(2192012*sizeof(uint32_t));
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fpgacode = (uint8_t *) malloc(2192012*sizeof(uint8_t));
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for(i = 0; i<2192012; i++){
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fscanf(mcs, "%d\n", &bitstream[i]);
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fpgacode[i] = bitstream[i];
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}
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fclose(mcs);
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// Get module IDs (PIC info)
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SG_PRINTF(INFO,"Getting module information.\n");
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ErrCode = (int32_t)sg_fpga_IO3xxGetModuleId(39750, &moduleId);
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if (ErrCode >= 0)
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{
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devname = moduleId.devname;
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moduleArchitecture = moduleId.moduleArchitecture;
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SG_PRINTF(DEBUG, "boardType: %d\n", 39750);
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SG_PRINTF(DEBUG, "ErrCode: %d\n", ErrCode);
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SG_PRINTF(DEBUG, "******************************************\n");
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SG_PRINTF(DEBUG, "moduleId->devname: %s\n", moduleId.devname);
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SG_PRINTF(DEBUG, "moduleId->vendorid: 0x%x\n", moduleId.vendorid);
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SG_PRINTF(DEBUG, "moduleId->subvendorid: 0x%x\n", moduleId.subvendorid);
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SG_PRINTF(DEBUG, "moduleId->deviceid: 0x%x\n", moduleId.deviceid);
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SG_PRINTF(DEBUG, "moduleId->subdeviceid: 0x%x\n", moduleId.subdeviceid);
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SG_PRINTF(DEBUG, "moduleId.moduleArchitecture: %d\n", moduleId.moduleArchitecture);
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}
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else
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{
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sprintf(msg, "Setup block: board type unknown.");
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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}
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// Support for different architectures
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SG_PRINTF(INFO,"Running board specific programming file.\n");
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switch (moduleArchitecture)
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{
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case TEWS_TPMC:
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ErrCode = IO30x_programFPGA(devname, (int16_t)-1, (int16_t)-1,
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(int32_t)1, (int32_t)1,
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(int32_t)0, (uint32_t)2192012, bitstream,
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&moduleId,(uint32_t)1102114075);
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break;
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case TEWS_TXMC:
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if (39750 == 324200 || 39750 == 334325 ||39750 == 336325 || 39750 == 325160)
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{
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ErrCode = IO324_programmFPGA(devname, (int16_t)-1,
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(int16_t)-1, (int32_t)1, (int32_t)1,
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(int32_t)0, (uint32_t)2192012, fpgacode,
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(uint32_t)1102114075, &moduleId, (uint32_t)85,
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(uint32_t)0);
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}
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else // IO31x, IO32x
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{
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ErrCode = IO31x_IO32x_programmFPGA(devname, (int16_t)-1,
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(int16_t)-1, (int32_t)1, (int32_t)1,
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(int32_t)0, (uint32_t)2192012, fpgacode,
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&moduleId, (uint32_t)85,(uint32_t)1102114075);
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}
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break;
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case ACROMAG_PMC:
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ErrCode = IO331_programmFPGA(devname, (int16_t)-1, (int16_t)-1,
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(int32_t)1, (int32_t)1,
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(uint32_t)2192012, bitstream, &moduleId);
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break;
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case ACROMAG_XMC:
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if (39750 == 332)
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{
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ErrCode = IO332_programmFPGA(devname, (int16_t)-1,
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(int16_t)-1, (int32_t)1, (int32_t)1,
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(uint32_t)2192012, bitstream, (uint32_t)1102114075,
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&moduleId);
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}
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else // IO333
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{
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ErrCode = IO333_programmFPGA(devname, (int16_t)-1,
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(int16_t)-1, (int32_t)1, (int32_t)1,
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(uint32_t)2192012, bitstream, (uint32_t)1102114075,
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&moduleId);
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}
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break;
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case TEWS_MPCIE:
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ErrCode = IO39x_programmFPGA(devname, (int16_t)-1, (int16_t)-1,
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(int32_t)1, (int32_t)1,
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(uint32_t)2192012, fpgacode, (uint32_t)85, &moduleId);
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break;
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case ENCLUSTRA_SOM:
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ErrCode = IO36x_programmFPGA(devname, (int16_t)-1, (int16_t)-1,
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(int32_t)1, (int32_t)1,
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(uint32_t)2192012, fpgacode,
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(uint32_t)85, (uint32_t)0, &moduleId);
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break;
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case XILINX_MPSOC:
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break;
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default:
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sprintf(msg, "Setup block: module architecture incorrect.");
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rtmSetErrorStatus(VFControl_M, msg);
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// Free the bitstream allocation
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SG_PRINTF(ERROR,msg);
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free(bitstream);
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free(fpgacode);
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return;
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}
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// Set board type (by now the board is registered)
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io3xxSetBoardTypeSgLib(1, 39750);
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// Free the bitstream allocation
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free(bitstream);
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free(fpgacode);
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// Handle any error states
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switch (ErrCode)
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{
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case NO_ERR:
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// Nothing to do.
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break;
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case BOARD_NOT_FOUND:
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// reason for this error can be found in the pSgErrorStr (error message from sg-lib (sg_findPciDevice))
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sprintf(msg, "%s", pSgErrorStr);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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case EEPROM_ERROR:
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sprintf(msg, "Setup block %s: Error updating board EEPROM.\n", devname);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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case REPROG_ERROR:
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sprintf(msg, "Setup block %s: Error writing new bitstream to FPGA.\n", devname);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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case FLASH_ERROR:
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sprintf(msg, "Setup block %s: Bitstream flash storage error.\n", devname);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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case BIST_ERROR:
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sprintf(msg, "Setup block %s: Built in self test error.\n", devname);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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case ICAP_RECONF_FAILED:
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sprintf(msg, "Setup block %s: ICAP Reconfiguration was not successful.\n",devname);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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case BOARD_TYPE_UNKNOWN:
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sprintf(msg, "Setup block %s: The board type selected is unknown.\n",devname);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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default:
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sprintf(msg, "Setup block %s: An unknown error occurred.\n",devname);
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rtmSetErrorStatus(VFControl_M, msg);
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SG_PRINTF(ERROR,msg);
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return;
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}
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// initialize Rear-IO's
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if (1 == 2){
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IO3xx_21_update(devname, 1, 0, 0, 0);
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}
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else if (1 == 3){
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IO3xx_22_update(devname, 1, 0, 0, 0);
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}
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else if (1 == 4){
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IO3xx_24_update(devname, 1, 0, 0, 0, 0);
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}
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// initial settings on module registry
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// Set all DIO's to registry inital values (all input, all output states = 0, all sources = codemodule)
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sg_fpga_io3xx_initDioLines(1, SG_FPGA_IO3XX_BAR2);
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// Set if FPGA DMA Controller is used
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ScatterGatherDmaState *sgDmaSharedState;
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sg_fpga_io3xx_getSharedSgDmaState(1, &sgDmaSharedState);
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sgDmaSharedState->useFpgaDmaController = 0;
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}
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{
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// run any code here at end of model-load
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// SG_PRINTF(INFO, "Setup Block: Entering TLC Trailer\n");
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// if(0){
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// io3xx_sgdma_finalizeDmaController(1);
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// io3xx_sgdma_startDmaController(1);
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// }
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}
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}
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__attribute__((constructor)) void early_init_setup(void)
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{
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sg_register_early_init_function(sg_init_sfcns);
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}
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