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No commits in common. "a2d05aa067ff48217660c219d56c5865db470197" and "04076e92921df836051a54c4429533fbd2cea3a7" have entirely different histories.

5 changed files with 4 additions and 9 deletions

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@ -80,8 +80,8 @@ def simular_LTS(tensionCap, Rtotal, Lbobina, Ctotal, lts_path, tSim = 100e-3, to
''' '''
modeloSim = "simulador/modelo_transitorio.asc" modeloSim = "src/simulador/modelo_transitorio.asc"
outDir = 'simulador' outDir = 'src/simulador'
## Hago la simulacion ## Hago la simulacion
@ -136,7 +136,7 @@ def dibujar(resultado):
if __name__ == '__main__': if __name__ == '__main__':
lts_path = "D:\\Appdata\\LTSpice\\LTSPice.exe" lts_path = "C:/Users/osuescuneli/AppData/Local/Programs/ADI/LTspice/LTspice.exe"
Tension = 30 Tension = 30
Resistencia = 10 Resistencia = 10

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@ -1,10 +1,5 @@
<<<<<<< HEAD
* C:\Users\pedro\Desktop\Projects\LaunchSim\src\simulador\modelo_transitorio.asc
* Generated by LTspice 24.1.4 for Windows.
=======
* C:\Users\osuescuneli\Desktop\practicas\Practia_Lanzadera\source\src\simulador\modelo_transitorio.asc * C:\Users\osuescuneli\Desktop\practicas\Practia_Lanzadera\source\src\simulador\modelo_transitorio.asc
* Generated by LTspice 24.1.5 for Windows. * Generated by LTspice 24.1.5 for Windows.
>>>>>>> 04076e92921df836051a54c4429533fbd2cea3a7
V1 N001 0 {V} V1 N001 0 {V}
S1 N001 condensador cont1 0 SW S1 N001 condensador cont1 0 SW
V2 cont1 0 PULSE(0 10 0 1n 1n {toff_sw} {tsim}) V2 cont1 0 PULSE(0 10 0 1n 1n {toff_sw} {tsim})
@ -17,7 +12,7 @@ V4 N002 N003 30
R2 N002 N003 20 R2 N002 N003 20
.model NMOS NMOS .model NMOS NMOS
.model PMOS PMOS .model PMOS PMOS
.lib C:\Users\pedro\AppData\Local\LTspice\lib\cmp\standard.mos .lib C:\Users\osuescuneli\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 {tsim} 0 .tran 0 {tsim} 0
.Model SW SW(Ron=1m Roff=100Meg Vt = 5) .Model SW SW(Ron=1m Roff=100Meg Vt = 5)
.param tsim 10 .param tsim 10